src/soc/intel/baytrail/elog.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_pm.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <elog.h>
   8 #include <soc/iomap.h>
   9 #include <soc/pm.h>
  10 #include <stdint.h>
  11
  12 static void log_power_and_resets(const struct chipset_power_state *ps)
  13 {
  14         if (ps->gen_pmcon1 & PWR_FLR) {
  15                 elog_add_event(ELOG_TYPE_POWER_FAIL);
  16                 elog_add_event(ELOG_TYPE_PWROK_FAIL);
  17         }
  18
  19         if (ps->gen_pmcon1 & SUS_PWR_FLR)
  20                 elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
  21
  22         if (ps->gen_pmcon1 & RPS)
  23                 elog_add_event(ELOG_TYPE_RTC_RESET);
  24
  25         if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS)
  26                 elog_add_event(ELOG_TYPE_TCO_RESET);
  27
  28         if (ps->pm1_sts & PRBTNOR_STS)
  29                 elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
  30
  31         if (ps->gen_pmcon1 & SRS)
  32                 elog_add_event(ELOG_TYPE_RESET_BUTTON);
  33
  34         if (ps->gen_pmcon1 & GEN_RST_STS)
  35                 elog_add_event(ELOG_TYPE_SYSTEM_RESET);
  36 }
  37
  38 static void log_wake_events(const struct chipset_power_state *ps)
  39 {
  40         const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS |
  41                                         PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS;
  42
  43         uint32_t gpe0_sts;
  44         uint32_t gpio_mask;
  45         int i;
  46
  47         /* Mask off disabled events. */
  48         gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
  49
  50         if (ps->pm1_sts & WAK_STS)
  51                 elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
  52                                     acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
  53
  54         if (ps->pm1_sts & PWRBTN_STS)
  55                 elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
  56
  57         if (ps->pm1_sts & RTC_STS)
  58                 elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
  59
  60         if (gpe0_sts & PME_B0_EN)
  61                 elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
  62
  63         if (gpe0_sts & pcie_wake_mask)
  64                 elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
  65
  66         gpio_mask = SUS_GPIO_STS0;
  67         i = 0;
  68         while (gpio_mask) {
  69                 if (gpio_mask & gpe0_sts)
  70                         elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
  71                 gpio_mask <<= 1;
  72                 i++;
  73         }
  74 }
  75
  76 void southcluster_log_state(void)
  77 {
  78         const struct chipset_power_state *ps;
  79
  80         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_ELOG) < 0)
  81                 return;
  82
  83         log_power_and_resets(ps);
  84         log_wake_events(ps);
  85 }