ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
[coreboot.git] / src / soc / intel / baytrail / emmc.c
blob3bfad01f4b278b7ccc3bc9e1467621e2ef3a7f82
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <reg_script.h>
9 #include <soc/device_nvs.h>
10 #include <soc/iosf.h>
11 #include <soc/pci_devs.h>
12 #include <soc/ramstage.h>
13 #include "chip.h"
15 static const struct reg_script emmc_ops[] = {
16 /* Enable 2ms card stable feature. */
17 REG_PCI_OR32(0xa8, (1 << 24)),
18 /* Enable HS200 */
19 REG_PCI_WRITE32(0xa0, 0x446cc801),
20 REG_PCI_WRITE32(0xa4, 0x80000807),
21 /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */
22 REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
23 /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */
24 REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
25 /* Set slew for HS200 */
26 REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
27 REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
28 /* Max timeout */
29 REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e),
30 REG_SCRIPT_END,
33 static void emmc_init(struct device *dev)
35 struct soc_intel_baytrail_config *config = config_of(dev);
37 printk(BIOS_DEBUG, "eMMC init\n");
38 reg_script_run_on_dev(dev, emmc_ops);
40 if (config->scc_acpi_mode)
41 scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC);
44 static struct device_operations device_ops = {
45 .read_resources = pci_dev_read_resources,
46 .set_resources = pci_dev_set_resources,
47 .enable_resources = pci_dev_enable_resources,
48 .init = emmc_init,
49 .ops_pci = &soc_pci_ops,
52 static const struct pci_driver southcluster __pci_driver = {
53 .ops = &device_ops,
54 .vendor = PCI_VID_INTEL,
55 .device = MMC45_DEVID,