src/soc/intel/baytrail/gfx.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <drivers/intel/gma/opregion.h>
  10 #include <reg_script.h>
  11 #include <soc/gfx.h>
  12 #include <soc/iosf.h>
  13 #include <soc/pci_devs.h>
  14 #include <soc/ramstage.h>
  15 #include <types.h>
  16
  17 #include "chip.h"
  18
  19 #define GFX_TIMEOUT 100000 /* 100ms */
  20
  21 /*
  22  * Lock Power Context Base Register to point to a 24KB block
  23  * of memory in GSM.  Power context save data is stored here.
  24  */
  25 static void gfx_lock_pcbase(struct device *dev)
  26 {
  27         struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
  28         const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
  29                                        288,320,352,384,416,448,480,512 };
  30         u32 pcsize = 24 << 10;  /* 24KB */
  31         u32 wopcmsz = 0x100000; /* PAVP offset */
  32         u32 gms, gmsize, pcbase;
  33
  34         gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK;
  35         gms >>= 3;
  36         if (gms >= ARRAY_SIZE(gms_size_map))
  37                 return;
  38         gmsize = gms_size_map[gms];
  39
  40         /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */
  41         pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000;
  42         pcbase += (gmsize-1) * wopcmsz - pcsize;
  43         pcbase |= 1; /* Lock */
  44
  45         write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase);
  46 }
  47
  48 static const struct reg_script gfx_init_script[] = {
  49         /* Allow-Wake render/media wells */
  50         REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1),
  51         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT),
  52         /* Render Force-Wake */
  53         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000),
  54         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000,
  55                        GFX_TIMEOUT),
  56         /* Media Force-Wake */
  57         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000),
  58         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000,
  59                        GFX_TIMEOUT),
  60         /* Workaround - X0:261954/A0:261955 */
  61         REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1),
  62
  63         /*
  64          * PowerMeter Weights
  65          */
  66
  67         /* SET1 */
  68         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000),
  69         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000),
  70         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A),
  71         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000),
  72         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900),
  73         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000),
  74         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000),
  75         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F),
  76         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000),
  77         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00),
  78         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016),
  79         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000),
  80         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100),
  81         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51),
  82         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000),
  83         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307),
  84         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000),
  85         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000),
  86         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000),
  87         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000),
  88         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800),
  89         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00),
  90         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021),
  91         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000),
  92         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000),
  93         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF),
  94         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000),
  95         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000),
  96         /* SET2 */
  97         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000),
  98         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000),
  99         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000),
 100         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000),
 101         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000),
 102         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000),
 103         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000),
 104         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F),
 105         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000),
 106         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00),
 107         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016),
 108         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000),
 109         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100),
 110         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51),
 111         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000),
 112         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307),
 113         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000),
 114         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000),
 115         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000),
 116         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000),
 117         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800),
 118         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000),
 119         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000),
 120         /* SET3 */
 121         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000),
 122         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000),
 123         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000),
 124         /* Enable PowerMeter Counters */
 125         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058),
 126
 127         /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
 128         /* SDP Profile 4 == 0x11940, others 0xcf08 */
 129         REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08),
 130
 131         /* GfxPause */
 132         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),
 133
 134         /* Dynamic EU Control Settings */
 135         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004),
 136
 137         /* Lock ECO Bit Settings */
 138         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000),
 139
 140         /* DOP Clock Gating */
 141         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001),
 142
 143         /* MBCunit will send the VCR (Fuse) writes as NP-W */
 144         REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000),
 145
 146         /*
 147          * RC6 Settings
 148          */
 149         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000),
 150         /* RC1e - RC6/6p - RC6pp Wake Rate Limits */
 151         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000),
 152         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848),
 153         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019),
 154         /* RC Sleep / RCx Thresholds */
 155         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000),
 156         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557),
 157
 158         /*
 159          * Turbo Settings
 160          */
 161
 162         /* Render/Video/Blitter Idle Max Count */
 163         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054,  0x0000000A),
 164         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A),
 165         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A),
 166         /* RP Down Timeout */
 167         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010,  0x000F4240),
 168
 169         /*
 170          * Turbo Control Settings
 171          */
 172
 173         /* RP Up/Down Threshold */
 174         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8),
 175         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08),
 176         /* RP Up/Down EI */
 177         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0),
 178         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730),
 179
 180         /* RP Idle Hysteresis */
 181         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
 182
 183         /* HW RC6 Control Settings */
 184         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000),
 185
 186         /* RP Control */
 187         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592),
 188
 189         /* Enable PM Interrupts */
 190         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000),
 191         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
 192         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e),
 193
 194         /* Aggressive Clock Gating */
 195         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0),
 196         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0),
 197         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0),
 198         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0),
 199
 200         /* Enable Gfx Turbo. */
 201         REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG,
 202                         ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0),
 203         REG_SCRIPT_END
 204 };
 205
 206 static const struct reg_script gpu_pre_vbios_script[] = {
 207         /* Make sure GFX is bus master with MMIO access */
 208         REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
 209         /* Display */
 210         REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
 211         REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
 212                       GFX_TIMEOUT),
 213         /* Tx/Rx Lanes */
 214         REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0),
 215         REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0,
 216                       GFX_TIMEOUT),
 217         /* Common Lane */
 218         REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0),
 219         REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0,
 220                       GFX_TIMEOUT),
 221         /* Ungating Tx only */
 222         REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0),
 223         REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0,
 224                       GFX_TIMEOUT),
 225         /* Ungating Common Lane only */
 226         REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0),
 227         REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0,
 228                       GFX_TIMEOUT),
 229         /* Ungating Display */
 230         REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000),
 231         REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000,
 232                       GFX_TIMEOUT),
 233         REG_SCRIPT_END
 234 };
 235
 236 static const struct reg_script gfx_post_vbios_script[] = {
 237         /* Deassert Render Force-Wake */
 238         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000),
 239         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT),
 240         /* Deassert Media Force-Wake */
 241         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000),
 242         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT),
 243         /* Set Lock bits */
 244         REG_PCI_RMW32(GGC, 0xffffffff, 1),
 245         REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1),
 246         REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1),
 247         REG_SCRIPT_END
 248 };
 249
 250 static inline void gfx_run_script(struct device *dev,
 251                                   const struct reg_script *ops)
 252 {
 253         reg_script_run_on_dev(dev, ops);
 254 }
 255
 256 static void gfx_pre_vbios_init(struct device *dev)
 257 {
 258         printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
 259         gfx_run_script(dev, gpu_pre_vbios_script);
 260 }
 261
 262 static void gfx_pm_init(struct device *dev)
 263 {
 264         printk(BIOS_INFO, "GFX: Power Management Init\n");
 265         gfx_run_script(dev, gfx_init_script);
 266
 267         /* Lock power context base */
 268         gfx_lock_pcbase(dev);
 269 }
 270
 271 static void gfx_post_vbios_init(struct device *dev)
 272 {
 273         printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
 274         gfx_run_script(dev, gfx_post_vbios_script);
 275 }
 276
 277 static void set_backlight_pwm(struct device *dev, uint32_t bklt_reg, int req_hz)
 278 {
 279         int divider;
 280         struct resource *res;
 281
 282         res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 283
 284         if (res == NULL)
 285                 return;
 286
 287         /* Default to 200 Hz if nothing is set. */
 288         if (req_hz == 0)
 289                 req_hz = 200;
 290
 291         /* Base clock is 25MHz */
 292         divider = 25 * 1000 * 1000 / (16 * req_hz);
 293
 294         /* Do not set duty cycle (lower 16 bits). Just set the divider. */
 295         write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);
 296 }
 297
 298 static void gfx_panel_setup(struct device *dev)
 299 {
 300         struct soc_intel_baytrail_config *config = config_of(dev);
 301         struct reg_script gfx_pipea_init[] = {
 302                 /* CONTROL */
 303                 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL),
 304                                 PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
 305                 /* POWER ON */
 306                 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS),
 307                                 ((u32)config->gpu_pipea_port_select << 30 |
 308                                  (u32)config->gpu_pipea_power_on_delay << 16 |
 309                                  (u32)config->gpu_pipea_light_on_delay)),
 310                 /* POWER OFF */
 311                 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS),
 312                                 ((u32)config->gpu_pipea_power_off_delay << 16 |
 313                                  (u32)config->gpu_pipea_light_off_delay)),
 314                 /* DIVISOR */
 315                 REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR),
 316                               ~0x1f, config->gpu_pipea_power_cycle_delay),
 317                 REG_SCRIPT_END
 318         };
 319         struct reg_script gfx_pipeb_init[] = {
 320                 /* CONTROL */
 321                 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL),
 322                                 PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
 323                 /* POWER ON */
 324                 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS),
 325                                 ((u32)config->gpu_pipeb_port_select << 30 |
 326                                  (u32)config->gpu_pipeb_power_on_delay << 16 |
 327                                  (u32)config->gpu_pipeb_light_on_delay)),
 328                 /* POWER OFF */
 329                 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS),
 330                                 ((u32)config->gpu_pipeb_power_off_delay << 16 |
 331                                  (u32)config->gpu_pipeb_light_off_delay)),
 332                 /* DIVISOR */
 333                 REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR),
 334                               ~0x1f, config->gpu_pipeb_power_cycle_delay),
 335                 REG_SCRIPT_END
 336         };
 337
 338         if (config->gpu_pipea_port_select) {
 339                 printk(BIOS_INFO, "GFX: Initialize PIPEA\n");
 340                 reg_script_run_on_dev(dev, gfx_pipea_init);
 341                 set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL),
 342                                   config->gpu_pipea_pwm_freq_hz);
 343         }
 344
 345         if (config->gpu_pipeb_port_select) {
 346                 printk(BIOS_INFO, "GFX: Initialize PIPEB\n");
 347                 reg_script_run_on_dev(dev, gfx_pipeb_init);
 348                 set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL),
 349                                   config->gpu_pipeb_pwm_freq_hz);
 350         }
 351 }
 352
 353 static void gfx_init(struct device *dev)
 354 {
 355         intel_gma_init_igd_opregion();
 356
 357         /* Pre VBIOS Init */
 358         gfx_pre_vbios_init(dev);
 359
 360         /* Power Management Init */
 361         gfx_pm_init(dev);
 362
 363         gfx_panel_setup(dev);
 364
 365         /* Run VBIOS */
 366         pci_dev_init(dev);
 367
 368         /* Post VBIOS Init */
 369         gfx_post_vbios_init(dev);
 370 }
 371
 372 static void gma_generate_ssdt(const struct device *dev)
 373 {
 374         const struct soc_intel_baytrail_config *chip = dev->chip_info;
 375
 376         drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 377 }
 378
 379 static struct device_operations gfx_device_ops = {
 380         .read_resources         = pci_dev_read_resources,
 381         .set_resources          = pci_dev_set_resources,
 382         .enable_resources       = pci_dev_enable_resources,
 383         .init                   = gfx_init,
 384         .ops_pci                = &soc_pci_ops,
 385         .acpi_fill_ssdt         = gma_generate_ssdt,
 386 };
 387
 388 static const struct pci_driver gfx_driver __pci_driver = {
 389         .ops    = &gfx_device_ops,
 390         .vendor = PCI_VID_INTEL,
 391         .device = GFX_DEVID,
 392 };