src/soc/intel/baytrail/lpss.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <reg_script.h>
  10
  11 #include <soc/iosf.h>
  12 #include <soc/nvs.h>
  13 #include <soc/device_nvs.h>
  14 #include <soc/pci_devs.h>
  15 #include <soc/ramstage.h>
  16
  17 #include "chip.h"
  18
  19 static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
  20 {
  21         struct reg_script ops[] = {
  22                 /* Disable PCI interrupt, enable Memory and Bus Master */
  23                 REG_PCI_OR16(PCI_COMMAND,
  24                              PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
  25                 /* Enable ACPI mode */
  26                 REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
  27                             LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
  28
  29                 REG_SCRIPT_END
  30         };
  31         struct resource *bar;
  32         struct device_nvs *dev_nvs = acpi_get_device_nvs();
  33
  34         /* Save BAR0 and BAR1 to ACPI NVS */
  35         bar = probe_resource(dev, PCI_BASE_ADDRESS_0);
  36         if (bar)
  37                 dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base;
  38
  39         bar = probe_resource(dev, PCI_BASE_ADDRESS_1);
  40         if (bar)
  41                 dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base;
  42
  43         /* Device is enabled in ACPI mode */
  44         dev_nvs->lpss_en[nvs_index] = 1;
  45
  46         /* Put device in ACPI mode */
  47         reg_script_run_on_dev(dev, ops);
  48 }
  49
  50 static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
  51 {
  52         struct reg_script ops[] = {
  53                 REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
  54                              ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP),
  55                              LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT),
  56                 REG_SCRIPT_END,
  57         };
  58
  59         reg_script_run_on_dev(dev, ops);
  60 }
  61
  62 #define SET_IOSF_REG(name_) \
  63         case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
  64                 do { \
  65                         *iosf_reg = LPSS_ ## name_ ## _CTL; \
  66                         *nvs_index = LPSS_NVS_ ## name_; \
  67                 } while (0)
  68
  69 static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
  70 {
  71         *iosf_reg = -1;
  72         *nvs_index = -1;
  73
  74         switch (dev->path.pci.devfn) {
  75         SET_IOSF_REG(SIO_DMA1);
  76                 break;
  77         SET_IOSF_REG(I2C1);
  78                 break;
  79         SET_IOSF_REG(I2C2);
  80                 break;
  81         SET_IOSF_REG(I2C3);
  82                 break;
  83         SET_IOSF_REG(I2C4);
  84                 break;
  85         SET_IOSF_REG(I2C5);
  86                 break;
  87         SET_IOSF_REG(I2C6);
  88                 break;
  89         SET_IOSF_REG(I2C7);
  90                 break;
  91         SET_IOSF_REG(SIO_DMA2);
  92                 break;
  93         SET_IOSF_REG(PWM1);
  94                 break;
  95         SET_IOSF_REG(PWM2);
  96                 break;
  97         SET_IOSF_REG(HSUART1);
  98                 break;
  99         SET_IOSF_REG(HSUART2);
 100                 break;
 101         SET_IOSF_REG(SPI);
 102                 break;
 103         }
 104 }
 105
 106 #define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
 107
 108 static void i2c_disable_resets(struct device *dev)
 109 {
 110         /* Release the I2C devices from reset. */
 111         static const struct reg_script ops[] = {
 112                 REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3),
 113                 REG_SCRIPT_END,
 114         };
 115
 116         switch (dev->path.pci.devfn) {
 117         CASE_I2C(I2C1):
 118         CASE_I2C(I2C2):
 119         CASE_I2C(I2C3):
 120         CASE_I2C(I2C4):
 121         CASE_I2C(I2C5):
 122         CASE_I2C(I2C6):
 123         CASE_I2C(I2C7):
 124                 printk(BIOS_DEBUG, "Releasing I2C device from reset.\n");
 125                 reg_script_run_on_dev(dev, ops);
 126                 break;
 127         default:
 128                 return;
 129         }
 130 }
 131
 132 static void lpss_init(struct device *dev)
 133 {
 134         struct soc_intel_baytrail_config *config = config_of(dev);
 135         int iosf_reg, nvs_index;
 136
 137         dev_ctl_reg(dev, &iosf_reg, &nvs_index);
 138
 139         if (iosf_reg < 0) {
 140                 int slot = PCI_SLOT(dev->path.pci.devfn);
 141                 int func = PCI_FUNC(dev->path.pci.devfn);
 142                 printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func);
 143                 return;
 144         }
 145         dev_enable_snoop_and_pm(dev, iosf_reg);
 146         i2c_disable_resets(dev);
 147
 148         if (config->lpss_acpi_mode)
 149                 dev_enable_acpi_mode(dev, iosf_reg, nvs_index);
 150 }
 151
 152 static struct device_operations device_ops = {
 153         .read_resources         = pci_dev_read_resources,
 154         .set_resources          = pci_dev_set_resources,
 155         .enable_resources       = pci_dev_enable_resources,
 156         .init                   = lpss_init,
 157         .ops_pci                = &soc_pci_ops,
 158 };
 159
 160 static const unsigned short pci_device_ids[] = {
 161         SIO_DMA1_DEVID,
 162         I2C1_DEVID,
 163         I2C2_DEVID,
 164         I2C3_DEVID,
 165         I2C4_DEVID,
 166         I2C5_DEVID,
 167         I2C6_DEVID,
 168         I2C7_DEVID,
 169         SIO_DMA2_DEVID,
 170         PWM1_DEVID,
 171         PWM2_DEVID,
 172         HSUART1_DEVID,
 173         HSUART2_DEVID,
 174         SPI_DEVID,
 175         0,
 176 };
 177
 178 static const struct pci_driver southcluster __pci_driver = {
 179         .ops            = &device_ops,
 180         .vendor         = PCI_VID_INTEL,
 181         .devices        = pci_device_ids,
 182 };