src/soc/intel/cannonlake/acpi/southbridge.asl

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /* PCR access */
   4 #include <soc/intel/common/acpi/pch_pcr.asl>
   5
   6 /* eMMC, SD Card */
   7 #include "scs.asl"
   8
   9 /* GPIO controller */
  10 #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
  11 #include "gpio_cnp_h.asl"
  12 #else
  13 #include "gpio.asl"
  14 #endif
  15
  16 /* LPC 0:1f.0 */
  17 #include <soc/intel/common/block/acpi/acpi/lpc.asl>
  18
  19 /* PCH HDA */
  20 #include "pch_hda.asl"
  21
  22 /* PCIE Ports */
  23 #include "pcie.asl"
  24
  25 /* Serial IO */
  26 #include "serialio.asl"
  27
  28 /* SMBus 0:1f.4 */
  29 #include <soc/intel/common/block/acpi/acpi/smbus.asl>
  30
  31 /* ISH 0:13.0 */
  32 #include <soc/intel/common/block/acpi/acpi/ish.asl>
  33
  34 /* USB XHCI 0:14.0 */
  35 #include "xhci.asl"
  36
  37 /* PCI _OSC */
  38 #include <soc/intel/common/acpi/pci_osc.asl>
  39
  40 /* GbE 0:1f.6 */
  41 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>