src/soc/intel/common/block/systemagent/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/romstage.h>
   4 #include <cbmem.h>
   5 #include <commonlib/bsd/helpers.h>
   6 #include <console/console.h>
   7 #include <cpu/x86/mtrr.h>
   8 #include <cpu/x86/smm.h>
   9 #include <intelbasecode/ramtop.h>
  10 #include <intelblocks/fast_spi.h>
  11 #include <intelblocks/systemagent.h>
  12 #include <types.h>
  13
  14 /*
  15  * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs):
  16  *
  17  * +---------------------------+ TOUUD
  18  * |                           |
  19  * +---------------------------+ TOM (if mem > 4GB)
  20  * | CSME UMA (if mem > 4 GiB) |
  21  * +---------------------------+ TOUUD
  22  * |                           |
  23  * +---------------------------+ 4GiB
  24  * | PCI Address Space         |
  25  * +---------------------------+ TOM (if mem < 4GB)
  26  * | CSME UMA (if mem < 4 GiB) |
  27  * +---------------------------+ TOLUD (also maps into MC address space)
  28  * | iGD / DSM                 |
  29  * +---------------------------+ BDSM
  30  * | GTT / GSM                 |
  31  * +---------------------------+ TOLM
  32  * | TSEG                      |
  33  * +---------------------------+ TSEGMB
  34  * | DMA Protected Region      |
  35  * +---------------------------+ DPR
  36  * | PRM (C6DRAM/SGX)          |
  37  * +---------------------------+ PRMRR
  38  * | Probeless Trace           |
  39  * +---------------------------+ ME Stolen
  40  * | PTT                       |
  41  * +---------------------------+ TOLUM / top_of_ram / cbmem_top
  42  * | CBMEM Root                |
  43  * +---------------------------+
  44  * | FSP Reserved Memory       |
  45  * +---------------------------+
  46  * | various CBMEM entries     |
  47  * +---------------------------+ top_of_stack (8 byte aligned)
  48  * | stack (CBMEM entry)       |
  49  * +---------------------------+ FSP TOLUM
  50  * |                           |
  51  * +---------------------------+ 0
  52  */
  53
  54 void smm_region(uintptr_t *start, size_t *size)
  55 {
  56         *start = sa_get_tseg_base();
  57         *size = sa_get_tseg_size();
  58 }
  59
  60 void fill_postcar_frame(struct postcar_frame *pcf)
  61 {
  62         /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */
  63         const uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 8 * MiB);
  64
  65         /*
  66          * We need to make sure ramstage will be run cached. At this
  67          * point exact location of ramstage in cbmem is not known.
  68          * Instruct postcar to cache 16 megs below cbmem top which is
  69          * a safe bet to cover ramstage.
  70          */
  71         printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
  72
  73         /*
  74          * Store the top_of_ram (ramtop) into the CMOS if SOC_INTEL_COMMON_BASECODE_RAMTOP
  75          * config is enabled.
  76          */
  77         if (ENV_CREATES_CBMEM && CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP))
  78                 update_ramtop(top_of_ram);
  79
  80         postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
  81
  82         /* Cache the TSEG region */
  83         postcar_enable_tseg_cache(pcf);
  84
  85         /* Cache the extended BIOS region if it is supported */
  86         fast_spi_cache_ext_bios_postcar(pcf);
  87 }