src/soc/intel/common/block/systemagent/systemagent_def.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H
   4 #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H
   5
   6 /* Device 0:0.0 PCI configuration space */
   7
   8 /* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */
   9 #define  DPR_EPM        (1 << 2)
  10 #define  DPR_PRS        (1 << 1)
  11 #define  DPR_SIZE_MASK  0xff0
  12 /* CAPID0_A */
  13 #define  CAPID_ECCDIS   (1 << 25)
  14 #define  CAPID_DDPCD    (1 << 14)
  15 #define  CAPID_PDCD     (1 << 12)
  16 #define  CAPID_DDRSZ(x) (((x) >> 19) & 0x3)
  17
  18 #define PAM0    0x80
  19 #define PAM1    0x81
  20 #define PAM2    0x82
  21 #define PAM3    0x83
  22 #define PAM4    0x84
  23 #define PAM5    0x85
  24 #define PAM6    0x86
  25
  26 /* PAM0 contains the lock bit */
  27 #define PAM_LOCK        (1 << 0)
  28
  29 /* Device 0:0.0 MMIO space */
  30 #define MCH_PAIR        0x5418
  31
  32 #define PCIEXBAR_LENGTH_MASK            0xE /* bits 1-3 */
  33 #define PCIEXBAR_LENGTH_MASK_LSB        1 /* used to shift right */
  34 #define DSM_LENGTH_MASK                 0xFF00 /* bits 8-15 */
  35 #define DSM_LENGTH_MASK_LSB             8 /* used to shift right */
  36 #define GSM_LENGTH_MASK                 0xC0 /* bits 6-7 */
  37 #define GSM_LENGTH_MASK_LSB             6 /* used to shift right */
  38 #define DPR_LENGTH_MASK                 0xFF0 /* bits 4-11 */
  39 #define DPR_LENGTH_MASK_LSB             4 /* used to shift right */
  40
  41 /*
  42  * IMR register in case CONFIG(SA_ENABLE_IMR) is selected by SoC.
  43  *
  44  * IMR registers are found under MCHBAR.
  45  */
  46 #define MCH_IMR0_BASE   0x6870
  47 #define MCH_IMR0_MASK   0x6874
  48 #define MCH_IMR_PITCH   0x20
  49 #define MCH_NUM_IMRS    20
  50
  51 /*
  52  * System Memory Map Registers
  53  * - top_of_ram -> TSEG - DPR: uncacheable
  54  * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved
  55  * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
  56  * - 4GiB -> TOUUD: cacheable
  57  */
  58 enum {
  59         SA_TOUUD_REG,
  60         SA_TOLUD_REG,
  61 #if CONFIG(HAVE_BDSM_BGSM_REGISTER)
  62         SA_BGSM_REG,
  63 #endif
  64         SA_TSEG_REG,
  65         /* Must be last. */
  66         MAX_MAP_ENTRIES
  67 };
  68
  69 /*
  70  * Set Fixed MMIO range
  71  *   REG = Either PCI configuration space registers.
  72  *   IS_64_BIT = If registers/offset is 64 bit.
  73  *   DESCRIPTION = Name of the register/offset.
  74  */
  75 struct sa_mem_map_descriptor {
  76         unsigned int reg;
  77         bool is_64_bit;
  78         const char *description;
  79 };
  80
  81 #endif  /* SOC_INTEL_COMMON_BLOCK_SA_DEF_H */