src/soc/intel/denverton_ns/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <bootstate.h>
   5 #include <cbfs.h>
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <fsp/api.h>
  10 #include <fsp/util.h>
  11 #include <gpio.h>
  12 #include <intelblocks/fast_spi.h>
  13 #include <intelblocks/acpi.h>
  14 #include <soc/iomap.h>
  15 #include <soc/intel/common/vbt.h>
  16 #include <soc/pci_devs.h>
  17 #include <soc/ramstage.h>
  18 #include <soc/fiamux.h>
  19 #include <spi-generic.h>
  20 #include <soc/hob_mem.h>
  21
  22 const char *soc_acpi_name(const struct device *dev)
  23 {
  24         if (dev->path.type == DEVICE_PATH_DOMAIN)
  25                 return "PCI0";
  26
  27         if (dev->path.type == DEVICE_PATH_USB) {
  28                 switch (dev->path.usb.port_type) {
  29                 case 0:
  30                         /* Root Hub */
  31                         return "RHUB";
  32                 case 2:
  33                         /* USB2 ports */
  34                         switch (dev->path.usb.port_id) {
  35                         case 0: return "HS01";
  36                         case 1: return "HS02";
  37                         case 2: return "HS03";
  38                         case 3: return "HS04";
  39                         }
  40                         break;
  41                 case 3:
  42                         /* USB3 ports */
  43                         switch (dev->path.usb.port_id) {
  44                         case 4: return "SS01";
  45                         case 5: return "SS02";
  46                         case 6: return "SS03";
  47                         case 7: return "SS04";
  48                         }
  49                         break;
  50                 }
  51                 return NULL;
  52         }
  53
  54         if (dev->path.type != DEVICE_PATH_PCI)
  55                 return NULL;
  56
  57         switch (dev->path.pci.devfn) {
  58         case SA_DEVFN_ROOT:
  59                 return "MCHC";
  60         case PCH_DEVFN_XHCI:
  61                 return "XHCI";
  62         case PCH_DEVFN_UART0:
  63                 return "UAR0";
  64         case PCH_DEVFN_UART1:
  65                 return "UAR1";
  66         case PCH_DEVFN_UART2:
  67                 return "UAR2";
  68         case PCH_DEVFN_PCIE1:
  69                 return "RP01";
  70         case PCH_DEVFN_PCIE2:
  71                 return "RP02";
  72         case PCH_DEVFN_PCIE3:
  73                 return "RP03";
  74         case PCH_DEVFN_PCIE4:
  75                 return "RP04";
  76         case PCH_DEVFN_PCIE5:
  77                 return "RP05";
  78         case PCH_DEVFN_PCIE6:
  79                 return "RP06";
  80         case PCH_DEVFN_PCIE7:
  81                 return "RP07";
  82         case PCH_DEVFN_PCIE8:
  83                 return "RP08";
  84         case PCH_DEVFN_LPC:
  85                 return "LPCB";
  86         case PCH_DEVFN_SMBUS:
  87                 return "SBUS";
  88         case PCH_DEVFN_SATA_0:
  89                 return "SAT0";
  90         case PCH_DEVFN_SATA_1:
  91                 return "SAT1";
  92         case PCH_DEVFN_EMMC:
  93                 return "EMMC";
  94         case PCH_DEVFN_SPI:
  95                 return "SPI0";
  96         case PCH_DEVFN_PMC:
  97                 return "PMC_";
  98         case PCH_DEVFN_QAT:
  99                 return "QAT_";
 100         case PCH_DEVFN_LAN0:
 101                 return "LAN0";
 102         case PCH_DEVFN_LAN1:
 103                 return "LAN1";
 104         }
 105
 106         return NULL;
 107 }
 108
 109 static struct device_operations pci_domain_ops = {
 110         .read_resources = &pci_domain_read_resources,
 111         .set_resources = &pci_domain_set_resources,
 112         .scan_bus = &pci_host_bridge_scan_bus,
 113 #if CONFIG(HAVE_ACPI_TABLES)
 114         .acpi_name = &soc_acpi_name,
 115 #endif
 116 };
 117
 118 static struct device_operations cpu_bus_ops = {
 119         .read_resources = noop_read_resources,
 120         .set_resources = noop_set_resources,
 121         .init = mp_cpu_bus_init,
 122 #if CONFIG(HAVE_ACPI_TABLES)
 123         .acpi_fill_ssdt = generate_cpu_entries,
 124 #endif
 125 };
 126
 127 static void soc_enable_dev(struct device *dev)
 128 {
 129         /* Set the operations if it is a special bus type */
 130         if (dev->path.type == DEVICE_PATH_DOMAIN)
 131                 dev->ops = &pci_domain_ops;
 132         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 133                 dev->ops = &cpu_bus_ops;
 134         else if (dev->path.type == DEVICE_PATH_GPIO)
 135                 block_gpio_enable(dev);
 136 }
 137
 138 static void soc_init(void *data)
 139 {
 140         fsp_silicon_init();
 141         soc_save_dimm_info();
 142 }
 143
 144 static void soc_final(void *data) {}
 145
 146 static void soc_silicon_init_params(FSPS_UPD *silupd)
 147 {
 148         size_t num;
 149         uint16_t supported_hsio_lanes;
 150         BL_HSIO_INFORMATION *hsio_config;
 151         BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data();
 152
 153         /* Configure FIA MUX PCD */
 154         supported_hsio_lanes =
 155                 (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed;
 156
 157         num = mainboard_get_hsio_config(&hsio_config);
 158
 159         if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config))
 160                 die("HSIO Configuration is invalid, please correct it!");
 161
 162         /* Initialize PCIE Bifurcation & HSIO configuration */
 163         silupd->FspsConfig.PcdBifurcationPcie0 = hsio_config->PcieBifCtr[0];
 164         silupd->FspsConfig.PcdBifurcationPcie1 = hsio_config->PcieBifCtr[1];
 165
 166         silupd->FspsConfig.PcdFiaMuxConfigRequestPtr =
 167                 (uint32_t)&hsio_config->FiaConfig;
 168 }
 169
 170 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 171 {
 172         const struct microcode *microcode_file;
 173         size_t microcode_len;
 174
 175         microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
 176
 177         if ((microcode_file != NULL) && (microcode_len != 0)) {
 178                 /* Update CPU Microcode patch base address/size */
 179                 silupd->FspsConfig.PcdCpuMicrocodePatchBase =
 180                        (uint32_t)microcode_file;
 181                 silupd->FspsConfig.PcdCpuMicrocodePatchSize =
 182                        (uint32_t)microcode_len;
 183         }
 184
 185         soc_silicon_init_params(silupd);
 186         mainboard_silicon_init_params(silupd);
 187 }
 188
 189 struct chip_operations soc_intel_denverton_ns_ops = {
 190         .name = "Intel Denverton-NS SOC",
 191         .enable_dev = soc_enable_dev,
 192         .init = soc_init,
 193         .final = soc_final
 194 };
 195
 196 struct pci_operations soc_pci_ops = {
 197         .set_subsystem = pci_dev_set_subsystem,
 198 };
 199
 200 /*
 201  * spi_flash init() needs to run unconditionally on every boot (including
 202  * resume) to allow write protect to be disabled for eventlog and nvram
 203  * updates. This needs to be done as early as possible in ramstage. Thus, add a
 204  * callback for entry into BS_PRE_DEVICE.
 205  */
 206 static void spi_flash_init_cb(void *unused)
 207 {
 208         fast_spi_init();
 209 }
 210
 211 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);