src/soc/intel/elkhartlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <commonlib/console/post_codes.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/mmio.h>
   8 #include <device/pci.h>
   9 #include <intelblocks/cse.h>
  10 #include <intelblocks/lpc_lib.h>
  11 #include <intelblocks/pcr.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelblocks/systemagent.h>
  14 #include <intelblocks/tco.h>
  15 #include <soc/p2sb.h>
  16 #include <soc/pci_devs.h>
  17 #include <soc/pcr_ids.h>
  18 #include <soc/pm.h>
  19 #include <soc/smbus.h>
  20 #include <soc/soc_chip.h>
  21 #include <soc/systemagent.h>
  22 #include <spi-generic.h>
  23
  24 static void pch_finalize(void)
  25 {
  26         /* TCO Lock down */
  27         tco_lockdown();
  28
  29         /* TODO: Add Thermal Configuration */
  30
  31         pmc_clear_pmcon_sts();
  32 }
  33
  34 static void heci_finalize(void)
  35 {
  36         heci_set_to_d0i3();
  37         if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
  38                 heci1_disable();
  39 }
  40
  41 static void soc_finalize(void *unused)
  42 {
  43         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  44
  45         pch_finalize();
  46         apm_control(APM_CNT_FINALIZE);
  47         if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
  48                  CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
  49                 heci_finalize();
  50
  51         /* Indicate finalize step with post code */
  52         post_code(POSTCODE_OS_BOOT);
  53 }
  54
  55 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
  56 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);