src/soc/intel/elkhartlake/lockdown.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <intelblocks/cfg.h>
   5 #include <intelpch/lockdown.h>
   6 #include <soc/pm.h>
   7
   8 static void pmc_lock_pmsync(void)
   9 {
  10         uint8_t *pmcbase;
  11         uint32_t pmsyncreg;
  12
  13         pmcbase = pmc_mmio_regs();
  14
  15         pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
  16         pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
  17         write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
  18 }
  19
  20 static void pmc_lock_abase(void)
  21 {
  22         uint8_t *pmcbase;
  23         uint32_t reg32;
  24
  25         pmcbase = pmc_mmio_regs();
  26
  27         reg32 = read32(pmcbase + GEN_PMCON_B);
  28         reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
  29         write32(pmcbase + GEN_PMCON_B, reg32);
  30 }
  31
  32 static void pmc_lock_smi(void)
  33 {
  34         uint8_t *pmcbase;
  35         uint8_t reg8;
  36
  37         pmcbase = pmc_mmio_regs();
  38
  39         reg8 = read8(pmcbase + GEN_PMCON_B);
  40         reg8 |= SMI_LOCK;
  41         write8(pmcbase + GEN_PMCON_B, reg8);
  42 }
  43
  44 static void pmc_lockdown_cfg(int chipset_lockdown)
  45 {
  46         /* PMSYNC */
  47         pmc_lock_pmsync();
  48         /* Lock down ABASE and sleep stretching policy */
  49         pmc_lock_abase();
  50
  51         if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
  52                 pmc_lock_smi();
  53 }
  54
  55 void soc_lockdown_config(int chipset_lockdown)
  56 {
  57         /* PMC lock down configuration */
  58         pmc_lockdown_cfg(chipset_lockdown);
  59 }