src/soc/intel/elkhartlake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 #define __SIMPLE_DEVICE__
   9
  10 #include <acpi/acpi_pm.h>
  11 #include <console/console.h>
  12 #include <device/device.h>
  13 #include <device/mmio.h>
  14 #include <device/pci.h>
  15 #include <gpio.h>
  16 #include <intelblocks/pmclib.h>
  17 #include <intelblocks/rtc.h>
  18 #include <intelblocks/tco.h>
  19 #include <intelpch/espi.h>
  20 #include <security/vboot/vbnv.h>
  21 #include <soc/gpe.h>
  22 #include <soc/iomap.h>
  23 #include <soc/pci_devs.h>
  24 #include <soc/pm.h>
  25 #include <soc/smbus.h>
  26 #include <soc/soc_chip.h>
  27 #include <static.h>
  28
  29 /*
  30  * SMI
  31  */
  32
  33 const char *const *soc_smi_sts_array(size_t *a)
  34 {
  35         static const char *const smi_sts_bits[] = {
  36                 [BIOS_STS_BIT] = "BIOS",
  37                 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
  38                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  39                 [APM_STS_BIT] = "APM",
  40                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  41                 [PM1_STS_BIT] = "PM1",
  42                 [GPE0_STS_BIT] = "GPE0",
  43                 [GPIO_STS_BIT] = "GPI",
  44                 [MCSMI_STS_BIT] = "MCSMI",
  45                 [DEVMON_STS_BIT] = "DEVMON",
  46                 [TCO_STS_BIT] = "TCO",
  47                 [PERIODIC_STS_BIT] = "PERIODIC",
  48                 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
  49                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  50                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  51                 [MONITOR_STS_BIT] = "MONITOR",
  52                 [SPI_SMI_STS_BIT] = "SPI",
  53                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
  54                 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
  55         };
  56
  57         *a = ARRAY_SIZE(smi_sts_bits);
  58         return smi_sts_bits;
  59 }
  60
  61 /*
  62  * TCO
  63  */
  64
  65 const char *const *soc_tco_sts_array(size_t *a)
  66 {
  67         static const char *const tco_sts_bits[] = {
  68                 [0] = "NMI2SMI",
  69                 [1] = "SW_TCO",
  70                 [2] = "TCO_INT",
  71                 [3] = "TIMEOUT",
  72                 [7] = "NEWCENTURY",
  73                 [8] = "BIOSWR",
  74                 [9] = "DMISCI",
  75                 [10] = "DMISMI",
  76                 [12] = "DMISERR",
  77                 [13] = "SLVSEL",
  78                 [16] = "INTRD_DET",
  79                 [17] = "SECOND_TO",
  80                 [18] = "BOOT",
  81                 [20] = "SMLINK_SLV"
  82         };
  83
  84         *a = ARRAY_SIZE(tco_sts_bits);
  85         return tco_sts_bits;
  86 }
  87
  88 /*
  89  * GPE0
  90  */
  91
  92 const char *const *soc_std_gpe_sts_array(size_t *a)
  93 {
  94         static const char *const gpe_sts_bits[] = {
  95                 [1] = "HOTPLUG",
  96                 [2] = "SWGPE",
  97                 [6] = "TCO_SCI",
  98                 [7] = "SMB_WAK",
  99                 [9] = "PCI_EXP",
 100                 [10] = "BATLOW",
 101                 [11] = "PME",
 102                 [12] = "ME",
 103                 [13] = "PME_B0",
 104                 [14] = "eSPI",
 105                 [15] = "GPIO Tier-2",
 106                 [16] = "LAN_WAKE",
 107                 [18] = "WADT"
 108         };
 109
 110         *a = ARRAY_SIZE(gpe_sts_bits);
 111         return gpe_sts_bits;
 112 }
 113
 114 void pmc_set_disb(void)
 115 {
 116         /* Set the DISB after DRAM init */
 117         uint8_t disb_val;
 118         /* Only care about bits [23:16] of register GEN_PMCON_A */
 119         uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
 120
 121         disb_val = read8(addr);
 122         disb_val |= (DISB >> 16);
 123
 124         /* Don't clear bits that are write-1-to-clear */
 125         disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
 126         write8(addr, disb_val);
 127 }
 128
 129 /*
 130  * PMC controller gets hidden from PCI bus
 131  * during FSP-Silicon init call. Hence PWRMBASE
 132  * can't be accessible using PCI configuration space
 133  * read/write.
 134  */
 135 uint8_t *pmc_mmio_regs(void)
 136 {
 137         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 138 }
 139
 140 uintptr_t soc_read_pmc_base(void)
 141 {
 142         return (uintptr_t)pmc_mmio_regs();
 143 }
 144
 145 uint32_t *soc_pmc_etr_addr(void)
 146 {
 147         return (uint32_t *)(soc_read_pmc_base() + ETR);
 148 }
 149
 150 static void pmc_gpe0_different_values(const struct soc_intel_elkhartlake_config *config)
 151 {
 152         bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
 153                          (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
 154                          (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
 155
 156         assert(result);
 157 }
 158
 159 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 160 {
 161         DEVTREE_CONST struct soc_intel_elkhartlake_config *config;
 162
 163         config = config_of_soc();
 164
 165         pmc_gpe0_different_values(config);
 166
 167         /* Assign to out variable */
 168         *dw0 = config->pmc_gpe0_dw0;
 169         *dw1 = config->pmc_gpe0_dw1;
 170         *dw2 = config->pmc_gpe0_dw2;
 171 }
 172
 173 static int rtc_failed(uint32_t gen_pmcon_b)
 174 {
 175         return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
 176 }
 177
 178 static void clear_rtc_failed(void)
 179 {
 180         clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
 181 }
 182
 183 static int check_rtc_failed(uint32_t gen_pmcon_b)
 184 {
 185         const int failed = rtc_failed(gen_pmcon_b);
 186         if (failed) {
 187                 clear_rtc_failed();
 188                 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
 189         }
 190
 191         return failed;
 192 }
 193
 194 int soc_get_rtc_failed(void)
 195 {
 196         const struct chipset_power_state *ps;
 197
 198         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 199                 return 1;
 200
 201         return check_rtc_failed(ps->gen_pmcon_b);
 202 }
 203
 204 int vbnv_cmos_failed(void)
 205 {
 206         return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 207 }
 208
 209 static inline int deep_s3_enabled(void)
 210 {
 211         uint32_t deep_s3_pol;
 212
 213         deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
 214         return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 215 }
 216
 217 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 218 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 219 {
 220         /*
 221          * Check for any power failure to determine if this a wake from
 222          * S5 because the PCH does not set the WAK_STS bit when waking
 223          * from a true G3 state.
 224          */
 225         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
 226                 prev_sleep_state = ACPI_S5;
 227
 228         /*
 229          * If waking from S3 determine if deep S3 is enabled. If not,
 230          * need to check both deep sleep well and normal suspend well.
 231          * Otherwise just check deep sleep well.
 232          */
 233         if (prev_sleep_state == ACPI_S3) {
 234                 /* PWR_FLR represents deep sleep power well loss. */
 235                 uint32_t mask = PWR_FLR;
 236
 237                 /* If deep s3 isn't enabled check the suspend well too. */
 238                 if (!deep_s3_enabled())
 239                         mask |= SUS_PWR_FLR;
 240
 241                 if (ps->gen_pmcon_a & mask)
 242                         prev_sleep_state = ACPI_S5;
 243         }
 244
 245         return prev_sleep_state;
 246 }
 247
 248 void soc_fill_power_state(struct chipset_power_state *ps)
 249 {
 250         uint8_t *pmc;
 251
 252         ps->tco1_sts = tco_read_reg(TCO1_STS);
 253         ps->tco2_sts = tco_read_reg(TCO2_STS);
 254
 255         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
 256
 257         pmc = pmc_mmio_regs();
 258         ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
 259         ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 260         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 261         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 262
 263         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 264                 ps->gen_pmcon_a, ps->gen_pmcon_b);
 265
 266         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 267                 ps->gblrst_cause[0], ps->gblrst_cause[1]);
 268 }
 269
 270 /* STM Support */
 271 uint16_t get_pmbase(void)
 272 {
 273         return (uint16_t)ACPI_BASE_ADDRESS;
 274 }
 275
 276 /*
 277  * Set which power state system will be after reapplying
 278  * the power (from G3 State)
 279  */
 280 void pmc_soc_set_afterg3_en(const bool on)
 281 {
 282         uint8_t reg8;
 283         uint8_t *const pmcbase = pmc_mmio_regs();
 284
 285         reg8 = read8(pmcbase + GEN_PMCON_A);
 286         if (on)
 287                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 288         else
 289                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 290         write8(pmcbase + GEN_PMCON_A, reg8);
 291 }