src/soc/intel/pantherlake/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <fsp/api.h>
   6 #include <fsp/util.h>
   7 #include <gpio.h>
   8 #include <intelblocks/acpi.h>
   9 #include <intelblocks/cfg.h>
  10 #include <intelblocks/cse.h>
  11 #include <intelblocks/irq.h>
  12 #include <intelblocks/itss.h>
  13 #include <intelblocks/p2sb.h>
  14 #include <intelblocks/pcie_rp.h>
  15 #include <intelblocks/systemagent.h>
  16 #include <intelblocks/tcss.h>
  17 #include <intelblocks/xdci.h>
  18 #include <soc/intel/common/reset.h>
  19 #include <soc/intel/common/vbt.h>
  20 #include <soc/iomap.h>
  21 #include <soc/p2sb.h>
  22 #include <soc/pci_devs.h>
  23 #include <soc/pcie.h>
  24 #include <soc/ramstage.h>
  25 #include <soc/soc_chip.h>
  26 #include <soc/tcss.h>
  27 #include <static.h>
  28
  29 #if CONFIG(HAVE_ACPI_TABLES)
  30 const char *soc_acpi_name(const struct device *dev)
  31 {
  32         if (dev->path.type == DEVICE_PATH_DOMAIN)
  33                 return "PCI0";
  34
  35         if (dev->path.type == DEVICE_PATH_USB) {
  36                 switch (dev->path.usb.port_type) {
  37                 case 0:
  38                         /* Root Hub */
  39                         return "RHUB";
  40                 case 2:
  41                         /* USB2 ports */
  42                         switch (dev->path.usb.port_id) {
  43                         case 0: return "HS01";
  44                         case 1: return "HS02";
  45                         case 2: return "HS03";
  46                         case 3: return "HS04";
  47                         case 4: return "HS05";
  48                         case 5: return "HS06";
  49                         case 6: return "HS07";
  50                         case 7: return "HS08";
  51                         }
  52                         break;
  53                 case 3:
  54                         /* USB3 ports */
  55                         switch (dev->path.usb.port_id) {
  56                         case 0: return "SS01";
  57                         case 1: return "SS02";
  58                         case 2: return "SS03";
  59                         case 3: return "SS04";
  60                         }
  61                         break;
  62                 }
  63                 printk(BIOS_ERR, "Missing ACPI Name for USB port_type=0x%x\n",
  64                                 dev->path.usb.port_type);
  65                 return NULL;
  66         }
  67         if (dev->path.type != DEVICE_PATH_PCI) {
  68                 printk(BIOS_ERR, "Missing ACPI Name for USB path_type=0x%x\n",
  69                                 dev->path.type);
  70                 return NULL;
  71         }
  72
  73         switch (dev->path.pci.devfn) {
  74         case PCI_DEVFN_ROOT:            return "MCHC";
  75         case PCI_DEVFN_IGD:             return "GFX0";
  76         case PCI_DEVFN_TCSS_XHCI:       return "TXHC";
  77         case PCI_DEVFN_TCSS_XDCI:       return "TXDC";
  78         case PCI_DEVFN_TCSS_DMA0:       return "TDM0";
  79         case PCI_DEVFN_TCSS_DMA1:       return "TDM1";
  80         case PCI_DEVFN_TBT0:            return "TRP0";
  81         case PCI_DEVFN_TBT1:            return "TRP1";
  82         case PCI_DEVFN_TBT2:            return "TRP2";
  83         case PCI_DEVFN_TBT3:            return "TRP3";
  84         case PCI_DEVFN_THC0:            return "THC0";
  85         case PCI_DEVFN_THC1:            return "THC1";
  86         case PCI_DEVFN_NPU:             return "NPU";
  87         case PCI_DEVFN_IPU:             return "IPU0";
  88         case PCI_DEVFN_ISH:             return "ISHB";
  89         case PCI_DEVFN_XHCI:            return "XHCI";
  90         case PCI_DEVFN_SRAM:            return "SRAM";
  91         case PCI_DEVFN_I2C0:            return "I2C0";
  92         case PCI_DEVFN_I2C1:            return "I2C1";
  93         case PCI_DEVFN_I2C2:            return "I2C2";
  94         case PCI_DEVFN_I2C3:            return "I2C3";
  95         case PCI_DEVFN_I2C4:            return "I2C4";
  96         case PCI_DEVFN_I2C5:            return "I2C5";
  97         case PCI_DEVFN_CSE:             return "HECI";
  98         case PCI_DEVFN_PCIE1:           return "RP01";
  99         case PCI_DEVFN_PCIE2:           return "RP02";
 100         case PCI_DEVFN_PCIE3:           return "RP03";
 101         case PCI_DEVFN_PCIE4:           return "RP04";
 102         case PCI_DEVFN_PCIE5:           return "RP05";
 103         case PCI_DEVFN_PCIE6:           return "RP06";
 104         case PCI_DEVFN_PCIE7:           return "RP07";
 105         case PCI_DEVFN_PCIE8:           return "RP08";
 106         case PCI_DEVFN_PCIE9:           return "RP09";
 107         case PCI_DEVFN_PCIE10:          return "RP10";
 108         case PCI_DEVFN_PCIE11:          return "RP11";
 109         case PCI_DEVFN_PCIE12:          return "RP12";
 110         case PCI_DEVFN_PMC:             return "PMC";
 111         case PCI_DEVFN_UART0:           return "UAR0";
 112         case PCI_DEVFN_UART1:           return "UAR1";
 113         case PCI_DEVFN_UART2:           return "UAR2";
 114         case PCI_DEVFN_GSPI0:           return "SPI0";
 115         case PCI_DEVFN_GSPI1:           return "SPI1";
 116         /* Keeping ACPI device name coherent with ec.asl */
 117         case PCI_DEVFN_ESPI:            return "LPCB";
 118         case PCI_DEVFN_SPI:             return "FSPI";
 119         case PCI_DEVFN_HDA:             return "HDAS";
 120         case PCI_DEVFN_SMBUS:           return "SBUS";
 121         case PCI_DEVFN_GBE:             return "GLAN";
 122         }
 123         printk(BIOS_ERR, "Missing ACPI Name for PCI: 00:%02x.%01x\n",
 124                         PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
 125         return NULL;
 126 }
 127 #endif
 128
 129 #if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)
 130 /* SoC override API to identify if ISH Firmware existed inside CSE FPT */
 131 bool soc_is_ish_partition_enabled(void)
 132 {
 133         struct device *ish = pcidev_path_on_root(PCI_DEVFN_ISH);
 134         uint16_t ish_pci_id = ish ? pci_read_config16(ish, PCI_DEVICE_ID) : 0xFFFF;
 135
 136         if (ish_pci_id == 0xFFFF)
 137                 return false;
 138
 139         return true;
 140 }
 141 #endif
 142
 143 /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
 144 static void soc_fill_gpio_pm_configuration(void)
 145 {
 146         uint8_t value[TOTAL_GPIO_COMM];
 147         const struct soc_intel_pantherlake_config *config = config_of_soc();
 148
 149         if (config->gpio_override_pm)
 150                 memcpy(value, config->gpio_pm, sizeof(value));
 151         else
 152                 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
 153
 154         gpio_pm_configure(value, TOTAL_GPIO_COMM);
 155 }
 156
 157 /* Enable tracehub in device tree */
 158 static void soc_enable_tracehub(void)
 159 {
 160         struct device *dev;
 161
 162         dev = pcidev_path_on_root(PCI_DEVFN_NPK);
 163         if (dev) {
 164                 dev->enabled = 1;
 165                 printk(BIOS_DEBUG, "Tracehub is enabled.\n");
 166         }
 167 }
 168
 169 void soc_init_pre_device(void *chip_info)
 170 {
 171         struct soc_intel_pantherlake_config *config = config_of_soc();
 172         if (config == NULL) {
 173                 printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n");
 174                 return;
 175         }
 176         /* Validate TBT image authentication */
 177         config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM,
 178                                         IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
 179
 180         if (CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB))
 181                 soc_enable_tracehub();
 182
 183         /* Perform silicon specific init. */
 184         fsp_silicon_init();
 185
 186          /* Display FIRMWARE_VERSION_INFO_HOB */
 187         fsp_display_fvi_version_hob();
 188
 189         soc_fill_gpio_pm_configuration();
 190
 191         /* Swap enabled PCI ports in device tree if needed. */
 192         pcie_rp_update_devicetree(get_pcie_rp_table());
 193
 194         /* Swap enabled TBT root ports in device tree if needed. */
 195         pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
 196
 197         /*
 198          * Earlier when coreboot used to send EOP at late as possible caused
 199          * issue of delayed response from CSE since CSE was busy loading payload.
 200          * To resolve the issue, EOP should be sent earlier than current sequence
 201          * in the boot sequence at BS_DEV_INIT.
 202          *
 203          * Intel CSE team recommends to send EOP close to FW init (between FSP-S
 204          * exit and current boot sequence) to reduce message response time from
 205          * CSE hence moving sending EOP to earlier stage.
 206          */
 207         if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) {
 208                 printk(BIOS_INFO, "Sending EOP early from SoC\n");
 209                 cse_send_end_of_post();
 210         }
 211 }
 212
 213 static void cpu_fill_ssdt(const struct device *dev)
 214 {
 215         if (!generate_pin_irq_map())
 216                 printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n");
 217
 218         generate_cpu_entries(dev);
 219 }
 220
 221 static void cpu_set_north_irqs(struct device *dev)
 222 {
 223         irq_program_non_pch();
 224 }
 225
 226 static struct device_operations pci_domain_ops = {
 227         .read_resources   = &pci_domain_read_resources,
 228         .set_resources    = &pci_domain_set_resources,
 229         .scan_bus         = &pci_host_bridge_scan_bus,
 230 #if CONFIG(HAVE_ACPI_TABLES)
 231         .acpi_name        = &soc_acpi_name,
 232         .acpi_fill_ssdt   = ssdt_set_above_4g_pci,
 233 #endif
 234 };
 235
 236 static struct device_operations cpu_bus_ops = {
 237         .read_resources   = noop_read_resources,
 238         .set_resources    = noop_set_resources,
 239         .enable_resources = cpu_set_north_irqs,
 240 #if CONFIG(HAVE_ACPI_TABLES)
 241         .acpi_fill_ssdt = cpu_fill_ssdt,
 242 #endif
 243 };
 244
 245 static void soc_enable(struct device *dev)
 246 {
 247         /*
 248          * Set the operations if it is a special bus type or a hidden PCI
 249          * device.
 250          */
 251         if (dev->path.type == DEVICE_PATH_DOMAIN)
 252                 dev->ops = &pci_domain_ops;
 253         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 254                 dev->ops = &cpu_bus_ops;
 255         else if (dev->path.type == DEVICE_PATH_PCI &&
 256                  dev->path.pci.devfn == PCI_DEVFN_PMC)
 257                 dev->ops = &pmc_ops;
 258         else if (dev->path.type == DEVICE_PATH_PCI &&
 259                  dev->path.pci.devfn == PCI_DEVFN_P2SB)
 260                 dev->ops = &pcd_p2sb_ops;
 261         else if (dev->path.type == DEVICE_PATH_PCI &&
 262                  dev->path.pci.devfn == PCI_DEVFN_P2SB2)
 263                 dev->ops = &pcd_p2sb_2_ops;
 264         else if (dev->path.type == DEVICE_PATH_GPIO)
 265                 block_gpio_enable(dev);
 266 }
 267
 268 static void soc_init_final_device(void *chip_info)
 269 {
 270         efi_return_status_t reset_status = fsp_get_pch_reset_status();
 271
 272         if (reset_status == FSP_SUCCESS)
 273                 return;
 274
 275         /* Handle any pending reset request from previously executed FSP APIs */
 276         fsp_handle_reset(reset_status);
 277
 278         /* Control shouldn't return here */
 279         fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE,
 280                          "Failed to handle the FSP reset request with error");
 281 }
 282
 283 struct chip_operations soc_intel_pantherlake_ops = {
 284         .name           = "Intel Pantherlake",
 285         .enable_dev     = &soc_enable,
 286         .init           = &soc_init_pre_device,
 287         .final          = &soc_init_final_device,
 288 };