1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef _SOC_PANTHERLAKE_CHIP_H_
4 #define _SOC_PANTHERLAKE_CHIP_H_
6 #include <device/pci_ids.h>
7 #include <drivers/i2c/designware/dw_i2c.h>
9 #include <intelblocks/cfg.h>
10 #include <intelblocks/gpio.h>
11 #include <intelblocks/gspi.h>
12 #include <intelblocks/power_limit.h>
13 #include <intelblocks/pcie_rp.h>
14 #include <intelblocks/tcss.h>
16 #include <soc/pci_devs.h>
18 #include <soc/serialio.h>
23 /* Define config parameters for In-Band ECC (IBECC). */
24 #define MAX_IBECC_REGIONS 8
26 #define MAX_SAGV_POINTS 4
27 #define MAX_HD_AUDIO_SDI_LINKS 2
29 /* In-Band ECC Operation Mode */
31 IBECC_MODE_PER_REGION
,
40 bool region_enable
[MAX_IBECC_REGIONS
];
41 uint16_t region_base
[MAX_IBECC_REGIONS
];
42 uint16_t region_mask
[MAX_IBECC_REGIONS
];
45 enum soc_intel_pantherlake_power_limits
{
50 PTL_POWER_LIMITS_COUNT
,
53 /* TDP values for different SKUs */
54 enum soc_intel_pantherlake_cpu_tdps
{
60 /* Mapping of different SKUs based on CPU ID and TDP values */
63 enum soc_intel_pantherlake_power_limits limits
;
64 enum soc_intel_pantherlake_cpu_tdps cpu_tdp
;
66 { PCI_DID_INTEL_PTL_U_ID_1
, PTL_U_1_CORE
, TDP_15W
},
67 { PCI_DID_INTEL_PTL_H_ID_1
, PTL_H_1_CORE
, TDP_25W
},
68 { PCI_DID_INTEL_PTL_H_ID_2
, PTL_H_1_CORE
, TDP_25W
},
69 { PCI_DID_INTEL_PTL_H_ID_3
, PTL_H_2_CORE
, TDP_25W
},
70 { PCI_DID_INTEL_PTL_H_ID_4
, PTL_H_2_CORE
, TDP_25W
},
73 /* Types of display ports */
86 DDI_ENABLE_DDC
= BIT(0), /* Display Data Channel */
87 DDI_ENABLE_HPD
= BIT(1), /* Hot Plug Detect */
91 * TODO: Update as per PTL spec
93 * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10,
94 * 254 - CPU Default , 255 - Auto.
96 enum pkgcstate_limit
{
106 LIMIT_CPUDEFAULT
= 254,
110 /* Bit values for use in LpmStateEnableMask. */
111 enum lpm_state_mask
{
120 LPM_S0iX_ALL
= LPM_S0i2_0
| LPM_S0i2_1
| LPM_S0i2_2
121 | LPM_S0i3_0
| LPM_S0i3_1
| LPM_S0i3_2
| LPM_S0i3_3
| LPM_S0i3_4
,
125 * As per definition from FSP header:
129 * - [3] through [5] are reserved
139 * Slew Rate configuration for Deep Package C States for VR domain.
140 * They are fast time divided by 2.
154 struct soc_intel_pantherlake_config
{
156 /* Common struct containing soc config data required by common code */
157 struct soc_intel_common_config common_soc_config
;
159 /* Common struct containing power limits configuration information */
160 struct soc_power_limits_config power_limits_config
[PTL_POWER_LIMITS_COUNT
];
162 /* Gpio group routed to each dword of the GPE0 block. Values are
163 * of the form PMC_GPP_[A:U] or GPD.
165 uint8_t pmc_gpe0_dw0
; /* GPE0_31_0 STS/EN */
166 uint8_t pmc_gpe0_dw1
; /* GPE0_63_32 STS/EN */
167 uint8_t pmc_gpe0_dw2
; /* GPE0_95_64 STS/EN */
169 /* Generic IO decode ranges */
175 /* Enable S0iX support */
177 /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
178 bool tcss_d3_cold_disable
;
179 /* Enable DPTF support */
182 /* Deep SX enable for both AC and DC */
183 bool deep_s3_enable_ac
;
184 bool deep_s3_enable_dc
;
185 bool deep_s5_enable_ac
;
186 bool deep_s5_enable_dc
;
188 /* Deep Sx Configuration
189 * DSX_EN_WAKE_PIN - Enable WAKE# pin
190 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
191 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin
193 uint32_t deep_sx_config
;
195 /* TCC activation offset */
198 /* In-Band ECC (IBECC) configuration */
199 struct ibecc_config ibecc
;
201 /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
202 * When enabled memory will be training at two different frequencies.
203 * 0:Disabled, 1:Enabled
210 /* System Agent dynamic frequency work points that memory will be training
211 * at the enabled frequencies. Possible work points are:
212 * 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3
215 SAGV_POINTS_0_1
= 0x03,
216 SAGV_POINTS_0_1_2
= 0x07,
217 SAGV_POINTS_0_1_2_3
= 0x0f,
220 /* Rank Margin Tool. true:Enable, false:Disable */
224 struct usb2_port_config usb2_ports
[CONFIG_SOC_INTEL_USB2_DEV_MAX
];
225 struct usb3_port_config usb3_ports
[CONFIG_SOC_INTEL_USB3_DEV_MAX
];
226 /* Wake Enable Bitmap for USB2 ports */
227 uint16_t usb2_wake_enable_bitmap
;
228 /* Wake Enable Bitmap for USB3 ports */
229 uint16_t usb3_wake_enable_bitmap
;
230 /* Program OC pins for TCSS */
231 struct tcss_port_config tcss_ports
[MAX_TYPE_C_PORTS
];
232 uint8_t tbt_pcie_port_disable
[4];
233 uint8_t tcss_cap_policy
[4];
234 /* Validate TBT firmware authenticated and loaded into IMR */
235 bool tbt_authentication
;
238 bool pch_hda_audio_link_hda_enable
;
239 bool pch_hda_dsp_enable
;
240 bool pch_hda_sdi_enable
[MAX_HD_AUDIO_SDI_LINKS
];
242 /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
248 } pch_hda_idisp_link_tmode
;
250 /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
252 HDA_LINKFREQ_48MHZ
= 3,
253 HDA_LINKFREQ_96MHZ
= 4,
254 } pch_hda_idisp_link_frequency
;
256 bool pch_hda_idisp_codec_enable
;
258 struct pcie_rp_config pcie_rp
[CONFIG_MAX_ROOT_PORTS
];
259 uint8_t pcie_clk_config_flag
[CONFIG_MAX_PCIE_CLOCK_SRC
];
281 } igd_dvmt50_pre_alloc
;
283 bool skip_ext_gfx_scan
;
285 /* Enable/Disable EIST. true:Enabled, false:Disabled */
289 * When enabled, this feature makes the SoC throttle when the power
290 * consumption exceeds the I_TRIP threshold.
292 * FSPs sets a by default I_TRIP threshold adapted to the current SoC
293 * and assuming a Voltage Regulator error accuracy of 6.5%.
295 bool enable_fast_vmode
[NUM_VR_DOMAINS
];
298 * Current Excursion Protection needs to be set for each VR domain
299 * in order to be able to enable fast Vmode.
301 bool cep_enable
[NUM_VR_DOMAINS
];
304 * VR Fast Vmode I_TRIP threshold.
305 * 0-255A in 1/4 A units. Example: 400 = 100A
306 * This setting overrides the default value set by FSPs when Fast VMode
309 uint16_t fast_vmode_i_trip
[NUM_VR_DOMAINS
];
312 * Power state current threshold 1.
313 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
314 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
315 * SA, [3] through [5] are Reserved.
317 uint16_t ps_cur_1_threshold
[NUM_VR_DOMAINS
];
320 * Power state current threshold 2.
321 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
322 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
323 * SA, [3] through [5] are Reserved.
325 uint16_t ps_cur_2_threshold
[NUM_VR_DOMAINS
];
328 * Power state current threshold 3.
329 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
330 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
331 * SA, [3] through [5] are Reserved.
333 uint16_t ps_cur_3_threshold
[NUM_VR_DOMAINS
];
336 * SerialIO device mode selection:
337 * PchSerialIoDisabled,
340 * PchSerialIoLegacyUart,
341 * PchSerialIoSkipInit
343 uint8_t serial_io_i2c_mode
[CONFIG_SOC_INTEL_I2C_DEV_MAX
];
344 uint8_t serial_io_gspi_mode
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
345 uint8_t serial_io_uart_mode
[CONFIG_SOC_INTEL_UART_DEV_MAX
];
347 * GSPIn Default Chip Select Mode:
351 uint8_t serial_io_gspi_cs_mode
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
353 * GSPIn Default Chip Select State:
357 uint8_t serial_io_gspi_cs_state
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
359 /* CNVi WiFi Core Enable/Disable */
362 /* CNVi BT Core Enable/Disable */
365 /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
366 bool cnvi_bt_audio_offload
;
368 /* Debug interface selection */
370 DEBUG_INTERFACE_RAM
= BIT(0),
371 DEBUG_INTERFACE_UART_8250IO
= BIT(1),
372 DEBUG_INTERFACE_USB3
= BIT(3),
373 DEBUG_INTERFACE_LPSS_SERIAL_IO
= BIT(4),
374 DEBUG_INTERFACE_TRACEHUB
= BIT(5),
375 } debug_interface_flag
;
378 * These GPIOs will be programmed by the IOM to handle biasing of the
379 * Type-C aux (SBU) signals when certain alternate modes are used.
380 * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
381 * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
382 * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
383 * (name often contains `AUXP_DC` or `_AUX_P`).
385 struct typec_aux_bias_pads typec_aux_bias_pads
[MAX_TYPE_C_PORTS
];
388 * SOC Aux orientation override:
389 * This is a bitfield that corresponds to up to 4 TCSS ports on PTL.
390 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
391 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
392 * on the motherboard.
394 uint16_t tcss_aux_ori
;
396 /* Connect Topology Command timeout value */
397 uint16_t itbt_connect_topology_timeout_in_ms
;
400 * Override GPIO PM configuration:
401 * 0: Use FSP default GPIO PM program,
402 * 1: coreboot to override GPIO PM program
404 uint8_t gpio_override_pm
;
407 * GPIO PM configuration: 0 to disable, 1 to enable power gating
409 * Bit 5: MISCCFG_GPSIDEDPCGEN
410 * Bit 4: MISCCFG_GPRCOMPCDLCGEN
411 * Bit 3: MISCCFG_GPRTCDLCGEN
412 * Bit 2: MISCCFG_GSXLCGEN
413 * Bit 1: MISCCFG_GPDPCGEN
414 * Bit 0: MISCCFG_GPDLCGEN
416 uint8_t gpio_pm
[TOTAL_GPIO_COMM
];
421 * 0:Disabled, 1:eDP, 2:MIPI DSI
423 uint8_t ddi_port_A_config
;
424 uint8_t ddi_port_B_config
;
426 /* Enable(1)/Disable(0) HPD/DDC */
427 uint8_t ddi_ports_config
[DDI_PORT_COUNT
];
430 * Override CPU flex ratio value:
431 * CPU ratio value controls the maximum processor non-turbo ratio.
432 * Valid Range 0 to 63.
434 * In general descriptor provides option to set default cpu flex ratio.
435 * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
436 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
438 * Only override CPU flex ratio if don't want to boot with non-turbo max.
440 uint8_t cpu_ratio_override
;
443 * Enable(true)/Disable(false) CPU Replacement check.
444 * Default false. Setting this to true to check CPU replacement.
446 bool cpu_replacement_check
;
448 /* ISA Serial Base selection. */
450 ISA_SERIAL_BASE_ADDR_3F8
,
451 ISA_SERIAL_BASE_ADDR_2F8
,
452 } isa_serial_uart_base
;
455 * Enable or Disable C1 C-state Auto Demotion & un-demotion
456 * The algorithm looks at the behavior of the wake up tracker, how
457 * often it is waking up, and based on that it demote the c-state.
458 * Default false. Set this to true in order to disable C1-state auto
460 * NOTE: Un-Demotion from Demoted C1 needs to be disabled when
461 * C1 C-state Auto Demotion is disabled.
463 bool disable_c1_state_auto_demotion
;
466 * Enable or Disable Package C-state Demotion.
467 * Default is set to false.
468 * Set this to true in order to disable Package C-state demotion.
469 * NOTE: Un-Demotion from demoted Package C-state needs to be disabled
470 * when auto demotion is disabled.
472 bool disable_package_c_state_demotion
;
474 /* Enable PCH to CPU energy report feature. */
475 bool pch_pm_energy_report_enable
;
477 /* Energy-Performance Preference (HWP feature) */
478 bool enable_energy_perf_pref
;
479 uint8_t energy_perf_pref_value
;
484 * SAGV Frequency per point in Mhz. 0 is Auto, otherwise holds the
485 * frequency value expressed as an integer. For example: 1867
487 uint16_t sagv_freq_mhz
[MAX_SAGV_POINTS
];
489 /* Gear Selection for SAGV points. 0: Auto, 1: Gear 1, 2: Gear 2, 4: Gear 4 */
490 uint8_t sagv_gear
[MAX_SAGV_POINTS
];
493 * Enable or Disable Reduced BasicMemoryTest size.
494 * Default is set to false.
495 * Set this to true in order to reduce BasicMemoryTest size
497 bool lower_basic_mem_test_size
;
499 /* Platform Power Pmax in Watts. Zero means automatic. */
500 uint16_t psys_pmax_watts
;
502 /* Platform Power Limit 2 in Watts. */
503 uint16_t psys_pl2_watts
;
505 /* Enable or Disable Acoustic Noise Mitigation feature */
506 bool enable_acoustic_noise_mitigation
;
507 /* Disable Fast Slew Rate for Deep Package C States for VR domains */
508 bool disable_fast_pkgc_ramp
[NUM_VR_DOMAINS
];
510 * Slew Rate configuration for Deep Package C States for VR domains
511 * as per `enum slew_rate` data type.
513 uint8_t slow_slew_rate_config
[NUM_VR_DOMAINS
];
515 uint16_t max_dram_speed_mts
;
519 typedef struct soc_intel_pantherlake_config config_t
;
521 #endif /* _SOC_PANTHERLAKE_CHIP_H_ */