src/soc/intel/pantherlake/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <cpu/cpu.h>
   5 #include <cpu/intel/common/common.h>
   6 #include <cpu/intel/microcode.h>
   7 #include <cpu/intel/smm_reloc.h>
   8 #include <cpu/intel/turbo.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <cpu/x86/mp.h>
  11 #include <cpu/x86/msr.h>
  12 #include <device/pci.h>
  13 #include <fsp/api.h>
  14 #include <intelblocks/acpi.h>
  15 #include <intelblocks/cpulib.h>
  16 #include <intelblocks/mp_init.h>
  17 #include <intelblocks/msr.h>
  18 #include <intelblocks/pmclib.h>
  19 #include <smbios.h>
  20 #include <soc/cpu.h>
  21 #include <soc/msr.h>
  22 #include <soc/pci_devs.h>
  23 #include <soc/soc_chip.h>
  24 #include <static.h>
  25
  26 bool cpu_soc_is_in_untrusted_mode(void)
  27 {
  28         msr_t msr;
  29
  30         msr = rdmsr(MSR_BIOS_DONE);
  31         return !!(msr.lo & ENABLE_IA_UNTRUSTED);
  32 }
  33
  34 void cpu_soc_bios_done(void)
  35 {
  36         msr_t msr;
  37
  38         msr = rdmsr(MSR_BIOS_DONE);
  39         msr.lo |= ENABLE_IA_UNTRUSTED;
  40         wrmsr(MSR_BIOS_DONE, msr);
  41 }
  42
  43 uint8_t get_supported_lpm_mask(void)
  44 {
  45         return LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2;
  46 }
  47
  48 static void soc_fsp_load(void)
  49 {
  50         fsps_load();
  51 }
  52
  53 static void configure_misc(void)
  54 {
  55         msr_t msr;
  56
  57         const struct soc_intel_pantherlake_config *conf = config_of_soc();
  58
  59         msr = rdmsr(IA32_MISC_ENABLE);
  60         msr.lo |= FAST_STRINGS_ENABLE_BIT;
  61         msr.lo |= TM1_TM2_EMTTM_ENABLE_BIT;
  62         wrmsr(IA32_MISC_ENABLE, msr);
  63
  64         /* Set EIST status */
  65         cpu_set_eist(conf->eist_enable);
  66
  67         /* Disable Thermal interrupts */
  68         msr.lo = 0;
  69         msr.hi = 0;
  70         wrmsr(IA32_THERM_INTERRUPT, msr);
  71
  72         /* Enable package critical interrupt only */
  73         msr.lo = CRITICAL_TEMP_INTERRUPT_ENABLE;
  74         msr.hi = 0;
  75         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
  76
  77         /* Enable PROCHOT and Power Performance Platform Override */
  78         msr = rdmsr(MSR_POWER_CTL);
  79         msr.lo |= ENABLE_BIDIR_PROCHOT;
  80         msr.lo |= VR_THERM_ALERT_DISABLE_LOCK;
  81         msr.lo |= PWR_PERF_PLATFORM_OVR;
  82         wrmsr(MSR_POWER_CTL, msr);
  83 }
  84
  85 enum core_type get_soc_cpu_type(void)
  86 {
  87         if (cpu_is_hybrid_supported())
  88                 return cpu_get_cpu_type();
  89
  90         return CPUID_CORE_TYPE_INTEL_CORE;
  91 }
  92
  93 bool soc_is_nominal_freq_supported(void)
  94 {
  95         return true;
  96 }
  97
  98 static void enable_x2apic(void)
  99 {
 100         if (!CONFIG(X2APIC_LATE_WORKAROUND))
 101                 return;
 102
 103         enable_lapic_mode(true);
 104 }
 105
 106 /* All CPUs including BSP will run the following function. */
 107 void soc_core_init(struct device *cpu)
 108 {
 109         /* Clear out pending MCEs */
 110         mca_configure();
 111
 112         enable_x2apic();
 113
 114         enable_lapic_tpr();
 115
 116         /* Configure Enhanced SpeedStep and Thermal Sensors */
 117         configure_misc();
 118
 119         enable_pm_timer_emulation();
 120
 121         /* Enable Direct Cache Access */
 122         configure_dca_cap();
 123
 124         /* Set energy policy */
 125         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 126
 127         const struct soc_intel_pantherlake_config *conf = config_of_soc();
 128         /* Set energy-performance preference */
 129         if (conf != NULL && conf->enable_energy_perf_pref) {
 130                 if (check_energy_perf_cap())
 131                         set_energy_perf_pref(conf->energy_perf_pref_value);
 132         }
 133
 134         /* Enable Turbo */
 135         enable_turbo();
 136
 137         /* Set core type in struct cpu_info */
 138         set_dev_core_type();
 139
 140         if (CONFIG(INTEL_TME) && is_tme_supported())
 141                 set_tme_core_activate();
 142
 143         if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) {
 144                 /* Disable 3-strike error */
 145                 disable_signaling_three_strike_event();
 146
 147                 set_aesni_lock();
 148
 149                 /* Enable VMX */
 150                 set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx);
 151
 152                 /* Feature control lock configure */
 153                 set_feature_ctrl_lock();
 154         }
 155 }
 156
 157 static void per_cpu_smm_trigger(void)
 158 {
 159         /* Relocate the SMM handler. */
 160         smm_relocate();
 161 }
 162
 163 static void pre_mp_init(void)
 164 {
 165         soc_fsp_load();
 166
 167         const struct soc_intel_pantherlake_config *conf = config_of_soc();
 168         if (conf == NULL) {
 169                 printk(BIOS_ERR, "Configuration could not be retrieved.\n");
 170                 return;
 171         }
 172         if (conf->enable_energy_perf_pref) {
 173                 if (check_energy_perf_cap())
 174                         enable_energy_perf_pref();
 175                 else
 176                         printk(BIOS_WARNING, "Energy Performance Preference not supported!\n");
 177         }
 178 }
 179
 180 static void post_mp_init(void)
 181 {
 182         /* Set Max Ratio */
 183         cpu_set_max_ratio();
 184
 185         /*
 186          * 1. Now that all APs have been relocated as well as the BSP let SMIs
 187          * start flowing.
 188          * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
 189          * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
 190          */
 191         global_smi_enable_no_pwrbtn();
 192 }
 193
 194 static const struct mp_ops mp_ops = {
 195         /*
 196          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 197          * that are set prior to ramstage.
 198          * Real MTRRs programming are being done after resource allocation.
 199          */
 200         .pre_mp_init = pre_mp_init,
 201         .get_cpu_count = get_cpu_count,
 202         .get_smm_info = smm_info,
 203         .get_microcode_info = get_microcode_info,
 204         .pre_mp_smm_init = smm_initialize,
 205         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 206         .relocation_handler = smm_relocation_handler,
 207         .post_mp_init = post_mp_init,
 208 };
 209
 210 void mp_init_cpus(struct bus *cpu_bus)
 211 {
 212         if (mp_init_with_smm(cpu_bus, &mp_ops))
 213                 printk(BIOS_ERR, "MP initialization failure.\n");
 214
 215         /* Thermal throttle activation offset */
 216         configure_tcc_thermal_target();
 217 }
 218
 219 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 220 {
 221         if (!CONFIG(CHROMEOS))
 222                 return 0;
 223         /*
 224          * Locked RO Descriptor Implications:
 225          *
 226          * - A locked descriptor signals the RO binary is fixed; the FIT will load the
 227          *   RO's microcode during system reset.
 228          * - Attempts to load newer microcode from the RW CBFS will cause a boot-time
 229          *   delay (~60ms, core-dependent), as the microcode must be reloaded on BSP+APs.
 230          * - The kernel can load microcode updates without impacting AP FW boot time.
 231          * - Skipping RW CBFS microcode loading is low-risk when the RO is locked,
 232          *   prioritizing fast boot times.
 233          */
 234         if (CONFIG(LOCK_MANAGEMENT_ENGINE) && current_patch_id)
 235                 return 1;
 236
 237         return 0;
 238 }
 239
 240 /* Override SMBIOS type 4 processor serial numbers */
 241 const char *smbios_processor_serial_number(void)
 242 {
 243         char *qdf = retrieve_soc_qdf_info_via_pmc_ipc();
 244
 245         if (qdf != NULL)
 246                 return qdf;
 247         else
 248                 return "";
 249 }