ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
[coreboot.git] / src / soc / intel / pantherlake / espi.c
blobd5b5cf93c9d4634f78ce139e217a5f3212c924fb
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pci.h>
4 #include <pc80/isa-dma.h>
5 #include <pc80/i8259.h>
6 #include <arch/ioapic.h>
7 #include <intelblocks/itss.h>
8 #include <intelblocks/lpc_lib.h>
9 #include <intelblocks/pcr.h>
10 #include <intelpch/espi.h>
11 #include <soc/iomap.h>
12 #include <soc/irq.h>
13 #include <soc/pci_devs.h>
14 #include <soc/pcr_ids.h>
15 #include <soc/soc_chip.h>
16 #include <static.h>
18 void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
20 const struct soc_intel_pantherlake_config *config = config_of_soc();
22 gen_io_dec[0] = config->gen1_dec;
23 gen_io_dec[1] = config->gen2_dec;
24 gen_io_dec[2] = config->gen3_dec;
25 gen_io_dec[3] = config->gen4_dec;
28 void lpc_soc_init(struct device *dev)
30 /* Legacy initialization */
31 isa_dma_init();
32 pch_misc_init();
34 /* Enable CLKRUN_EN for power gating ESPI */
35 lpc_enable_pci_clk_cntl();
37 /* Set ESPI Serial IRQ mode */
38 if (CONFIG(SERIRQ_CONTINUOUS_MODE))
39 lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
40 else
41 lpc_set_serirq_mode(SERIRQ_QUIET);
43 /* Interrupt configuration */
44 pch_enable_ioapic();
45 pch_pirq_init();
46 setup_i8259();
47 i8259_configure_irq_trigger(9, 1);