src/soc/intel/pantherlake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootmode.h>
   4 #include <cpu/intel/microcode.h>
   5 #include <fsp/api.h>
   6 #include <fsp/fsp_debug_event.h>
   7 #include <fsp/fsp_gop_blt.h>
   8 #include <fsp/ppi/mp_service_ppi.h>
   9 #include <intelblocks/irq.h>
  10 #include <intelblocks/mp_init.h>
  11 #include <intelblocks/systemagent.h>
  12 #include <intelblocks/xdci.h>
  13 #include <intelpch/lockdown.h>
  14 #include <option.h>
  15 #include <soc/cpu.h>
  16 #include <soc/intel/common/vbt.h>
  17 #include <soc/pcie.h>
  18 #include <soc/ramstage.h>
  19 #include <static.h>
  20
  21 #define MAX_ONBOARD_PCIE_DEVICES 256
  22
  23 /* THC assignment definition */
  24 enum {
  25         THC_NONE,
  26         THC_0,
  27         THC_1
  28 };
  29
  30 /* LPSS UART Power Gating mode */
  31 enum {
  32         LPSS_UART_PG_DISABLED,
  33         LPSS_UART_PG_ENABLED,
  34         LPSS_UART_PG_AUTO
  35 };
  36
  37 static const pci_devfn_t i2c_dev[] = {
  38         PCI_DEVFN_I2C0,
  39         PCI_DEVFN_I2C1,
  40         PCI_DEVFN_I2C2,
  41         PCI_DEVFN_I2C3,
  42         PCI_DEVFN_I2C4,
  43         PCI_DEVFN_I2C5,
  44 };
  45
  46 static const pci_devfn_t uart_dev[] = {
  47         PCI_DEVFN_UART0,
  48         PCI_DEVFN_UART1,
  49         PCI_DEVFN_UART2
  50 };
  51
  52 static const pci_devfn_t gspi_dev[] = {
  53         PCI_DEVFN_GSPI0,
  54         PCI_DEVFN_GSPI1,
  55         PCI_DEVFN_GSPI2
  56 };
  57
  58 /*
  59  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  60  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
  61  * In order to ensure that mainboard setting does not disable L1 substates
  62  * incorrectly, chip config parameter values are offset by 1 with 0 meaning
  63  * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
  64  * value is set in fsp_params.
  65  * 0: Use FSP UPD default
  66  * 1: Disable L1 substates
  67  * 2: Use L1.1
  68  * 3: Use L1.2 (FSP UPD default)
  69  */
  70 static int get_l1_substate_control(enum L1_substates_control ctl)
  71 {
  72         if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
  73                 ctl = L1_SS_DISABLED;
  74         else if (ctl > L1_SS_L1_2 || ctl == L1_SS_FSP_DEFAULT)
  75                 ctl = L1_SS_L1_2;
  76         return ctl - 1;
  77 }
  78
  79 /*
  80  * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
  81  * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
  82  * that the mainboard setting does not disable ASPM incorrectly, chip
  83  * config parameter values are offset by 1 with 0 meaning use FSP UPD default.
  84  * get_aspm_control() ensures that the right UPD value is set in fsp_params.
  85  * 0: Use FSP UPD default
  86  * 1: Disable ASPM
  87  * 2: L0s only
  88  * 3: L1 only
  89  * 4: L0s and L1
  90  * 5: Auto configuration
  91  */
  92 static unsigned int get_aspm_control(enum ASPM_control ctl)
  93 {
  94         if (ctl > ASPM_AUTO || ctl == ASPM_DEFAULT)
  95                 ctl = ASPM_AUTO;
  96         return ctl - 1;
  97 }
  98
  99 __weak void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 100 {
 101         /* Override settings per board. */
 102 }
 103
 104 static const struct slot_irq_constraints irq_constraints[] = {
 105         {
 106                 .slot = PCI_DEV_SLOT_IGD,
 107                 .fns = {
 108                         /* INTERRUPT_PIN is RO/0x01 */
 109                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_IGD, PCI_INT_A),
 110                 },
 111         },
 112         {
 113                 .slot = PCI_DEV_SLOT_DPTF,
 114                 .fns = {
 115                         /* Dynamic Tuning Technology (DTT) device IRQ is not
 116                            programmable and is INT_A/PIRQ_A (IRQ 16) */
 117                         FIXED_INT_PIRQ(PCI_DEVFN_DPTF, PCI_INT_A, PIRQ_A),
 118                 },
 119         },
 120         {
 121                 .slot = PCI_DEV_SLOT_IPU,
 122                 .fns = {
 123                         /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW,
 124                            but S0ix fails when not set to 16 (b/193434192) */
 125                         FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A),
 126                 },
 127         },
 128         {
 129                 .slot = PCI_DEV_SLOT_PCIE_2,
 130                 .fns = {
 131                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
 132                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
 133 #if CONFIG(SOC_INTEL_PANTHERLAKE_H)
 134                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
 135                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
 136 #endif
 137                 },
 138         },
 139         {
 140                 .slot = PCI_DEV_SLOT_TBT,
 141                 .fns = {
 142                         ANY_PIRQ(PCI_DEVFN_TBT0),
 143                         ANY_PIRQ(PCI_DEVFN_TBT1),
 144                         ANY_PIRQ(PCI_DEVFN_TBT2),
 145                         ANY_PIRQ(PCI_DEVFN_TBT3),
 146                 },
 147         },
 148         {
 149                 .slot = PCI_DEV_SLOT_NPU,
 150                 .fns = {
 151                         /* INTERRUPT_PIN is RO/0x01 */
 152                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPU, PCI_INT_A),
 153                 },
 154         },
 155         {
 156                 .slot = PCI_DEV_SLOT_TCSS,
 157                 .fns = {
 158                         ANY_PIRQ(PCI_DEVFN_TCSS_XHCI),
 159                 },
 160         },
 161         {
 162                 .slot = PCI_DEV_SLOT_THC,
 163                 .fns = {
 164                         ANY_PIRQ(PCI_DEVFN_THC0),
 165                         ANY_PIRQ(PCI_DEVFN_THC1),
 166                 },
 167         },
 168         {
 169                 .slot = PCI_DEV_SLOT_ISH,
 170                 .fns = {
 171                         DIRECT_IRQ(PCI_DEVFN_ISH),
 172                 },
 173         },
 174         {
 175                 .slot = PCI_DEV_SLOT_XHCI,
 176                 .fns = {
 177                         ANY_PIRQ(PCI_DEVFN_XHCI),
 178                         DIRECT_IRQ(PCI_DEVFN_USBOTG),
 179                         ANY_PIRQ(PCI_DEVFN_CNVI_WIFI),
 180                 },
 181         },
 182         {
 183                 .slot = PCI_DEV_SLOT_SIO0,
 184                 .fns = {
 185                         DIRECT_IRQ(PCI_DEVFN_I2C0),
 186                         DIRECT_IRQ(PCI_DEVFN_I2C1),
 187                         DIRECT_IRQ(PCI_DEVFN_I2C2),
 188                         DIRECT_IRQ(PCI_DEVFN_I2C3),
 189                 },
 190         },
 191         {
 192                 .slot = PCI_DEV_SLOT_CSE,
 193                 .fns = {
 194                         ANY_PIRQ(PCI_DEVFN_CSE),
 195                         ANY_PIRQ(PCI_DEVFN_CSE_2),
 196                         ANY_PIRQ(PCI_DEVFN_CSE_IDER),
 197                         ANY_PIRQ(PCI_DEVFN_CSE_KT),
 198                         ANY_PIRQ(PCI_DEVFN_CSE_3),
 199                         ANY_PIRQ(PCI_DEVFN_CSE_4),
 200                 },
 201         },
 202 #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
 203         {
 204                 .slot = PCI_DEV_SLOT_UFS,
 205                 .fns = {
 206                         ANY_PIRQ(PCI_DEVFN_UFS),
 207                 },
 208         },
 209 #endif
 210         {
 211                 .slot = PCI_DEV_SLOT_SIO1,
 212                 .fns = {
 213                         DIRECT_IRQ(PCI_DEVFN_I2C4),
 214                         DIRECT_IRQ(PCI_DEVFN_I2C5),
 215                         DIRECT_IRQ(PCI_DEVFN_UART2),
 216                 },
 217         },
 218         {
 219                 .slot = PCI_DEV_SLOT_PCIE_1,
 220                 .fns = {
 221                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
 222                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
 223                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
 224                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
 225                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
 226                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
 227                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
 228                         FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
 229                 },
 230         },
 231         {
 232                 .slot = PCI_DEV_SLOT_SIO2,
 233                 .fns = {
 234                         /* UART0 shares an interrupt line with TSN0, so must use
 235                            a PIRQ */
 236                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART0, PCI_INT_A),
 237                         /* UART1 shares an interrupt line with TSN1, so must use
 238                            a PIRQ */
 239                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART1, PCI_INT_B),
 240                         DIRECT_IRQ(PCI_DEVFN_GSPI0),
 241                         DIRECT_IRQ(PCI_DEVFN_GSPI1),
 242                 },
 243         },
 244         {
 245                 .slot = PCI_DEV_SLOT_ESPI,
 246                 .fns = {
 247                         ANY_PIRQ(PCI_DEVFN_HDA),
 248                         ANY_PIRQ(PCI_DEVFN_SMBUS),
 249                         ANY_PIRQ(PCI_DEVFN_GBE),
 250                         /* INTERRUPT_PIN is RO/0x01 */
 251                         FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPK, PCI_INT_A),
 252                 },
 253         },
 254 };
 255
 256 static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
 257                                   const struct soc_intel_pantherlake_config *config)
 258 {
 259         size_t i;
 260
 261         for (i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
 262                 s_cfg->SerialIoI2cMode[i] =
 263                         is_devfn_enabled(i2c_dev[i]) ? config->serial_io_i2c_mode[i] : 0;
 264
 265         for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
 266                 s_cfg->SerialIoLpssSpiCsMode[i] = config->serial_io_gspi_cs_mode[i];
 267                 s_cfg->SerialIoLpssSpiCsState[i] = config->serial_io_gspi_cs_state[i];
 268                 s_cfg->SerialIoLpssSpiMode[i] =
 269                         is_devfn_enabled(gspi_dev[i]) ? config->serial_io_gspi_mode[i] : 0;
 270         }
 271
 272         for (i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) {
 273                 s_cfg->SerialIoUartMode[i] = is_devfn_enabled(uart_dev[i]) ?
 274                         config->serial_io_uart_mode[i] : 0;
 275                 s_cfg->SerialIoUartPowerGating[i] = is_devfn_enabled(uart_dev[i]) ?
 276                         LPSS_UART_PG_ENABLED : LPSS_UART_PG_AUTO;
 277         }
 278 }
 279
 280 static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
 281                                  const struct soc_intel_pantherlake_config *config)
 282 {
 283         if (!CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
 284                 return;
 285
 286         s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
 287 }
 288
 289 static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg,
 290                                  const struct soc_intel_pantherlake_config *config)
 291 {
 292         const struct microcode *microcode;
 293         size_t length;
 294
 295         if (!CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS))
 296                 return;
 297
 298         /* Locate microcode and pass to FSP-S for 2nd microcode loading */
 299         microcode = intel_microcode_find();
 300         if (!microcode)
 301                 return;
 302
 303         length = get_microcode_size(microcode);
 304         if (!length)
 305                 return;
 306
 307         /* Update CPU Microcode patch base address/size */
 308         s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode;
 309         s_cfg->MicrocodeRegionSize = (uint32_t)length;
 310 }
 311
 312 static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
 313                                  const struct soc_intel_pantherlake_config *config)
 314 {
 315         /* Load VBT before devicetree-specific config. */
 316         s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get();
 317
 318         /* Check if IGD is present and fill Graphics init param accordingly */
 319         s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD);
 320         s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
 321         s_cfg->PavpEnable = CONFIG(PAVP);
 322 }
 323
 324 static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 325                                   const struct soc_intel_pantherlake_config *config)
 326 {
 327         s_cfg->TcssAuxOri = config->tcss_aux_ori;
 328
 329         /* Explicitly clear this field to avoid using defaults */
 330         memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
 331
 332         /* D3Cold for TCSS */
 333         s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable;
 334         s_cfg->UsbTcPortEn = 0;
 335
 336         for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++)
 337                 if (config->tcss_ports[i].enable)
 338                         s_cfg->UsbTcPortEn |= BIT(i);
 339 }
 340
 341 static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
 342                                               const struct soc_intel_pantherlake_config *config)
 343 {
 344         /* Chipset Lockdown */
 345         const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
 346
 347         s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp;
 348         s_cfg->PchLockDownBiosInterface = lockdown_by_fsp;
 349         s_cfg->PchUnlockGpioPads = !lockdown_by_fsp;
 350         s_cfg->RtcMemoryLock = lockdown_by_fsp;
 351         s_cfg->SkipPamLock = !lockdown_by_fsp;
 352
 353         /* coreboot will send EOP before loading payload */
 354         s_cfg->EndOfPostMessage = 0; /* EOP disable */
 355
 356         s_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG);
 357 }
 358
 359 static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
 360                                   const struct soc_intel_pantherlake_config *config)
 361 {
 362         size_t i;
 363
 364         for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) {
 365                 s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable;
 366                 s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
 367                 s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
 368                 s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
 369                 s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 370
 371                 if (config->usb2_ports[i].enable)
 372                         s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
 373                 else
 374                         s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
 375
 376                 s_cfg->PortResetMessageEnable[i] = config->usb2_ports[i].type_c;
 377         }
 378
 379         for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) {
 380                 s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 381                 if (config->usb3_ports[i].enable)
 382                         s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 383                 else
 384                         s_cfg->Usb3OverCurrentPin[i] = OC_SKIP;
 385
 386                 if (config->usb3_ports[i].tx_de_emp) {
 387                         s_cfg->Usb3HsioTxDeEmphEnable[i] = 1;
 388                         s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 389                 }
 390                 if (config->usb3_ports[i].tx_downscale_amp) {
 391                         s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 392                         s_cfg->Usb3HsioTxDownscaleAmp[i] =
 393                                 config->usb3_ports[i].tx_downscale_amp;
 394                 }
 395         }
 396
 397         for (i = 0; i < MAX_TYPE_C_PORTS; i++)
 398                 if (config->tcss_ports[i].enable)
 399                         s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
 400 }
 401
 402 static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
 403                                   const struct soc_intel_pantherlake_config *config)
 404 {
 405         s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG);
 406 }
 407
 408 static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg,
 409                                      const struct soc_intel_pantherlake_config *config)
 410 {
 411         s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF);
 412 }
 413
 414 static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
 415 {
 416         const struct pci_irq_entry *entry = get_cached_pci_irqs();
 417         SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
 418         size_t pch_total = 0, cfg_count = 0;
 419
 420         if (!entry)
 421                 return NULL;
 422
 423         /* Count PCH devices */
 424         while (entry) {
 425                 if (is_pch_slot(entry->devfn))
 426                         pch_total++;
 427                 entry = entry->next;
 428         }
 429
 430         /* Convert PCH device entries to FSP format */
 431         config = calloc(pch_total, sizeof(*config));
 432         entry = get_cached_pci_irqs();
 433         while (entry) {
 434                 if (!is_pch_slot(entry->devfn)) {
 435                         entry = entry->next;
 436                         continue;
 437                 }
 438
 439                 config[cfg_count].Device = PCI_SLOT(entry->devfn);
 440                 config[cfg_count].Function = PCI_FUNC(entry->devfn);
 441                 config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
 442                 config[cfg_count].Irq = entry->irq;
 443                 cfg_count++;
 444
 445                 entry = entry->next;
 446         }
 447
 448         *out_count = cfg_count;
 449
 450         return config;
 451 }
 452
 453 static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
 454                                  const struct soc_intel_pantherlake_config *config)
 455 {
 456         if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
 457                 die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n");
 458
 459         size_t pch_count = 0;
 460         const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
 461
 462         s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
 463         s_cfg->NumOfDevIntConfig = pch_count;
 464         printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 465 }
 466
 467 static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid)
 468 {
 469         if (!(dev && svid && ssid))
 470                 return;
 471
 472         *svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086);
 473         *ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0xfffe);
 474 }
 475
 476 /*
 477  * Programming SSID before FSP-S is important because SSID registers of a few PCIE
 478  * devices (e.g. IPU, Crashlog, XHCI, TCSS_XHCI etc.) are locked after FSP-S hence
 479  * provide a custom SSID (same as DID by default) value via UPD.
 480  */
 481 static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg,
 482                                       const struct soc_intel_pantherlake_config *config)
 483 {
 484         struct svid_ssid_init_entry {
 485                 union {
 486                         struct {
 487                                 uint64_t reg:12;
 488                                 uint64_t function:3;
 489                                 uint64_t device:5;
 490                                 uint64_t bus:8;
 491                                 uint64_t ignore1:4;
 492                                 uint64_t segment:16;
 493                                 uint64_t ignore2:16;
 494                         };
 495                         uint64_t data;
 496                 };
 497                 struct {
 498                         uint16_t svid;
 499                         uint16_t ssid;
 500                 };
 501                 uint32_t ignore3;
 502         };
 503
 504         static struct svid_ssid_init_entry ssid_table[MAX_ONBOARD_PCIE_DEVICES];
 505         const struct device *dev;
 506         size_t i = 0;
 507
 508         for (dev = all_devices; dev; dev = dev->next) {
 509                 if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI &&
 510                     dev->upstream->secondary == 0))
 511                         continue;
 512
 513                 if (dev->path.pci.devfn == PCI_DEVFN_ROOT) {
 514                         evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid);
 515                 } else {
 516                         ssid_table[i].reg       = PCI_SUBSYSTEM_VENDOR_ID;
 517                         ssid_table[i].device    = PCI_SLOT(dev->path.pci.devfn);
 518                         ssid_table[i].function  = PCI_FUNC(dev->path.pci.devfn);
 519                         evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid);
 520                         i++;
 521                 }
 522         }
 523
 524         s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table;
 525         s_cfg->SiNumberOfSsidTableEntry = i;
 526
 527         /* Ensure FSP will program the registers */
 528         s_cfg->SiSkipSsidProgramming = 0;
 529 }
 530
 531 static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg,
 532                                  const struct soc_intel_pantherlake_config *config)
 533 {
 534         s_cfg->PchLanEnable = is_devfn_enabled(PCI_DEVFN_GBE);
 535 }
 536
 537 static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 538                                   const struct soc_intel_pantherlake_config *config)
 539 {
 540         s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI);
 541         s_cfg->CnviWifiCore = config->cnvi_wifi_core;
 542         s_cfg->CnviBtCore = config->cnvi_bt_core;
 543         s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload;
 544
 545         if (!s_cfg->CnviMode && s_cfg->CnviWifiCore) {
 546                 printk(BIOS_ERR, "CNVi WiFi is enabled without CNVi being enabled\n");
 547                 s_cfg->CnviWifiCore = 0;
 548         }
 549         if (!s_cfg->CnviBtCore && s_cfg->CnviBtAudioOffload) {
 550                 printk(BIOS_ERR, "BT offload is enabled without CNVi BT being enabled\n");
 551                 s_cfg->CnviBtAudioOffload = 0;
 552         }
 553         if (!s_cfg->CnviMode && s_cfg->CnviBtCore) {
 554                 printk(BIOS_ERR, "CNVi BT is enabled without CNVi being enabled\n");
 555                 s_cfg->CnviBtCore = 0;
 556                 s_cfg->CnviBtAudioOffload = 0;
 557         }
 558
 559         s_cfg->CnviBtInterface = is_devfn_enabled(PCI_DEVFN_CNVI_BT) ? 2 : 1;
 560 }
 561
 562 static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg,
 563                                    const struct soc_intel_pantherlake_config *config)
 564 {
 565         s_cfg->PmcPdEnable = 1;
 566 }
 567
 568 static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg,
 569                                  const struct soc_intel_pantherlake_config *config)
 570 {
 571         s_cfg->ThcAssignment[0] = is_devfn_enabled(PCI_DEVFN_THC0) ? THC_0 : THC_NONE;
 572         s_cfg->ThcAssignment[1] = is_devfn_enabled(PCI_DEVFN_THC1) ? THC_1 : THC_NONE;
 573 }
 574
 575 static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
 576                                   const struct soc_intel_pantherlake_config *config)
 577 {
 578         bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
 579         s_cfg->Enable8254ClockGating = !use_8254;
 580         s_cfg->Enable8254ClockGatingOnS3 = !use_8254;
 581 }
 582
 583 static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
 584                                       const struct soc_intel_pantherlake_config *config)
 585 {
 586         /*
 587          * Legacy PM ACPI Timer (and TCO Timer)
 588          * This *must* be 1 in any case to keep FSP from
 589          *  1) enabling PM ACPI Timer emulation in uCode.
 590          *  2) disabling the PM ACPI Timer.
 591          * We handle both by ourself!
 592          */
 593         s_cfg->EnableTcoTimer = 1;
 594 }
 595
 596 static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 597                                   const struct soc_intel_pantherlake_config *config)
 598 {
 599         uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table());
 600
 601         for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 602                 const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];
 603                 if (!(enable_mask & BIT(i)))
 604                         continue;
 605                 s_cfg->PcieRpL1Substates[i] =
 606                         get_l1_substate_control(rp_cfg->PcieRpL1Substates);
 607                 s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
 608                 s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
 609                 s_cfg->PcieRpHotPlug[i] =
 610                         !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 611                 s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 612                 if (rp_cfg->pcie_rp_aspm)
 613                         s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
 614         }
 615
 616         s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 617 }
 618
 619 static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 620                                         const struct soc_intel_pantherlake_config *config)
 621 {
 622         /* Skip setting D0I3 bit for all HECI devices */
 623         s_cfg->DisableD0I3SettingForHeci = 1;
 624
 625         s_cfg->Hwp = 1;
 626         s_cfg->Cx = 1;
 627         /* Enable the energy efficient turbo mode */
 628         s_cfg->EnergyEfficientTurbo = 1;
 629         s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
 630         /* Un-Demotion from Demoted C1 need to be disable when
 631            C1 auto demotion is disabled. */
 632         s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion;
 633         s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
 634         s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion;
 635         s_cfg->PkgCStateUnDemotion = !config->disable_package_c_state_demotion;
 636         s_cfg->PmcV1p05PhyExtFetControlEn = 1;
 637
 638         /* Enable/Disable PCH to CPU energy report feature. */
 639         s_cfg->PchPmDisableEnergyReport = !config->pch_pm_energy_report_enable;
 640 }
 641
 642 static void fill_fsps_npu_params(FSP_S_CONFIG *s_cfg,
 643                                  const struct soc_intel_pantherlake_config *config)
 644 {
 645         s_cfg->NpuEnable = is_devfn_enabled(PCI_DEVFN_NPU);
 646 }
 647
 648 static void fill_fsps_audio_params(FSP_S_CONFIG *s_cfg,
 649                                    const struct soc_intel_pantherlake_config *config)
 650 {
 651         if (!is_devfn_enabled(PCI_DEVFN_HDA))
 652                 return;
 653
 654         /* Fill MIC privacy settings */
 655         s_cfg->PchHdaMicPrivacyHwModeSoundWire0 = 1;
 656         s_cfg->PchHdaMicPrivacyHwModeSoundWire1 = 1;
 657         s_cfg->PchHdaMicPrivacyHwModeSoundWire2 = 1;
 658         s_cfg->PchHdaMicPrivacyHwModeSoundWire3 = 1;
 659         s_cfg->PchHdaMicPrivacyHwModeSoundWire4 = 1;
 660         s_cfg->PchHdaMicPrivacyHwModeDmic = 1;
 661 }
 662
 663 static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,
 664                                  const struct soc_intel_pantherlake_config *config)
 665 {
 666         s_cfg->IaxEnable = is_devfn_enabled(PCI_DEVFN_IAA);
 667 }
 668
 669 static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg,
 670                 const struct soc_intel_pantherlake_config *config)
 671 {
 672 #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
 673         /* Setting FSP UPD (1,0) to enable controller 0 */
 674         s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS);
 675         s_cfg->UfsEnable[1] = 0;
 676 #else
 677         /* Setting FSP UPD (0,0) to keep both controllers disabled */
 678         s_cfg->UfsEnable[0] = 0;
 679         s_cfg->UfsEnable[1] = 0;
 680 #endif
 681 }
 682
 683 static void arch_silicon_init_params(FSPS_ARCH2_UPD *s_arch_cfg)
 684 {
 685         /* Assign FspEventHandler arch Upd to use coreboot debug event handler */
 686         if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)
 687             && CONFIG(CONSOLE_SERIAL)
 688             && CONFIG(FSP_ENABLE_SERIAL_DEBUG))
 689                 s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)
 690                                                           fsp_debug_event_handler);
 691
 692 }
 693
 694 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 695                                     const struct soc_intel_pantherlake_config *config)
 696 {
 697         void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg,
 698                                    const struct soc_intel_pantherlake_config *config) = {
 699                 fill_fsps_lpss_params,
 700                 fill_fsps_cpu_params,
 701                 fill_fsps_microcode_params,
 702                 fill_fsps_igd_params,
 703                 fill_fsps_tcss_params,
 704                 fill_fsps_chipset_lockdown_params,
 705                 fill_fsps_xhci_params,
 706                 fill_fsps_xdci_params,
 707                 fill_fsps_thermal_params,
 708                 fill_fsps_irq_params,
 709                 fill_fsps_pci_ssid_params,
 710                 fill_fsps_lan_params,
 711                 fill_fsps_cnvi_params,
 712                 fill_fsps_pmcpd_params,
 713                 fill_fsps_thc_params,
 714                 fill_fsps_8254_params,
 715                 fill_fsps_pm_timer_params,
 716                 fill_fsps_pcie_params,
 717                 fill_fsps_misc_power_params,
 718                 fill_fsps_npu_params,
 719                 fill_fsps_audio_params,
 720                 fill_fsps_iax_params,
 721                 fill_fsps_ufs_params,
 722         };
 723
 724         for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)
 725                 fill_fsps_params[i](s_cfg, config);
 726 }
 727
 728 /* UPD parameters to be initialized before SiliconInit */
 729 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 730 {
 731         struct soc_intel_pantherlake_config *config;
 732         FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
 733         FSPS_ARCH2_UPD *s_arch_cfg = &supd->FspsArchUpd;
 734
 735         config = config_of_soc();
 736         arch_silicon_init_params(s_arch_cfg);
 737         /* Override settings per board if required. */
 738         mainboard_update_soc_chip_config(config);
 739         soc_silicon_init_params(s_cfg, config);
 740         mainboard_silicon_init_params(s_cfg);
 741 }
 742
 743 /*
 744  * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
 745  * This platform supports below MultiPhaseSIInit Phase(s):
 746  *
 747  * Phase |  FSP return point                    |  Purpose
 748  * ----- + -------------------------------------+ ------------------------
 749  *   1   |  After TCSS initialization completed |  for TCSS specific init
 750  */
 751 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
 752 {
 753         switch (phase_index) {
 754         case 1:
 755                 /* TCSS specific initialization here */
 756                 printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
 757                        __FILE__, __func__);
 758
 759                 if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
 760                         const struct soc_intel_pantherlake_config *config = config_of_soc();
 761                         tcss_configure(config->typec_aux_bias_pads);
 762                 }
 763                 break;
 764         default:
 765                 break;
 766         }
 767 }
 768
 769 /* Mainboard GPIO Configuration */
 770 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 771 {
 772         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 773 }
 774
 775 /* Handle FSP logo params */
 776 void soc_load_logo(FSPS_UPD *supd)
 777 {
 778         efi_uintn_t logo, blt_size;
 779         uint32_t logo_size;
 780
 781         fsp_convert_bmp_to_gop_blt(&logo, &logo_size,
 782                                    &supd->FspsConfig.BltBufferAddress,
 783                                    &blt_size,
 784                                    &supd->FspsConfig.LogoPixelHeight,
 785                                    &supd->FspsConfig.LogoPixelWidth);
 786 }