1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <intelblocks/gpio.h>
4 #include <intelblocks/pcr.h>
5 #include <soc/pcr_ids.h>
8 static const struct reset_mapping rst_map
[] = {
9 { .logical
= PAD_RESET(PWROK
), .chipset
= 0U << 30 },
10 { .logical
= PAD_RESET(DEEP
), .chipset
= 1U << 30 },
11 { .logical
= PAD_RESET(PLTRST
), .chipset
= 2U << 30 },
12 { .logical
= PAD_RESET(GLBRST
), .chipset
= 3U << 30 },
16 * The GPIO pinctrl driver for Panther Lake on Linux expects 32 GPIOs per pad
17 * group, regardless of whether or not there is a physical pad for each
18 * exposed GPIO number.
20 * This results in the OS having a sparse GPIO map, and devices that need
21 * to export an ACPI GPIO must use the OS expected number.
23 * Not all pins are usable as GPIO and those groups do not have a pad base.
25 static const struct pad_group ptl_community0_groups
[] = {
26 INTEL_GPP_BASE(GPP_V00
, GPP_V00
, GPP_RST_B
, 0), /* GPP_V */
27 INTEL_GPP_BASE(GPP_V00
, GPP_C00
, GPP_C23
, 32), /* GPP_C */
30 static const struct pad_group ptl_community1_groups
[] = {
31 INTEL_GPP_BASE(GPP_F00
, GPP_F00
, GPP_GSPI0_CLK_LOOPBK
, 0), /* GPP_F */
32 INTEL_GPP_BASE(GPP_F00
, GPP_E00
, GPP_THC0_GSPI_CLK_LPBK
, 32), /* GPP_E */
35 static const struct pad_group ptl_community3_groups
[] = {
36 INTEL_GPP(GPP_EPD_ON
, GPP_EPD_ON
, GPP_DDSP_HPDALV
), /* GPP_CPUJTAG */
37 INTEL_GPP_BASE(GPP_EPD_ON
, GPP_H00
, GPP_ISHI3C1_CLK_LPBK
, 32), /* GPP_H */
38 INTEL_GPP_BASE(GPP_EPD_ON
, GPP_A00
, GPP_SPI0_CLK_LOOPBK
, 64), /* GPP_A */
39 INTEL_GPP(GPP_EPD_ON
, GPP_VGPIO3_USB0
, GPP_VGPIO3_THC3
), /* GPP_VGPIO_3*/
42 static const struct pad_group ptl_community4_groups
[] = {
43 INTEL_GPP_BASE(GPP_S00
, GPP_S00
, GPP_S07
, 0), /* GPP_S */
46 static const struct pad_group ptl_community5_groups
[] = {
47 INTEL_GPP_BASE(GPP_B00
, GPP_B00
, GPP_ISHI3C0_CLK_LPBK
, 0), /* GPP_B */
48 INTEL_GPP_BASE(GPP_B00
, GPP_D00
, GPP_D25
, 32), /* GPP_D */
49 INTEL_GPP(GPP_B00
, GPP_VGPIO0
, GPP_VGPIO47
), /* GPP_VGPIO */
52 static const struct pad_community ptl_communities
[] = {
53 [COMM_0
] = { /* GPP V,C */
55 .first_pad
= COM0_GRP_PAD_START
,
56 .last_pad
= COM0_GRP_PAD_END
,
57 .num_gpi_regs
= NUM_GPIO_COM0_GPI_REGS
,
58 .pad_cfg_base
= PAD_CFG_BASE
,
59 .pad_cfg_lock_offset
= PAD_CFG_LOCK_REG_0
,
60 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
61 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
62 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
63 .gpi_gpe_sts_reg_0
= GPI_GPE_STS_0
,
64 .gpi_gpe_en_reg_0
= GPI_GPE_EN_0
,
65 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
66 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
67 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
69 .acpi_path
= "\\_SB.PCI0.GPI0",
71 .num_reset_vals
= ARRAY_SIZE(rst_map
),
72 .groups
= ptl_community0_groups
,
73 .num_groups
= ARRAY_SIZE(ptl_community0_groups
),
75 [COMM_1
] = { /* GPP: F, E */
77 .first_pad
= COM1_GRP_PAD_START
,
78 .last_pad
= COM1_GRP_PAD_END
,
79 .num_gpi_regs
= NUM_GPIO_COM1_GPI_REGS
,
80 .pad_cfg_base
= PAD_CFG_BASE
,
81 .pad_cfg_lock_offset
= PAD_CFG_LOCK_REG_0
,
82 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
83 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
84 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
85 .gpi_gpe_sts_reg_0
= GPI_GPE_STS_0
,
86 .gpi_gpe_en_reg_0
= GPI_GPE_EN_0
,
87 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
88 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
89 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
91 .acpi_path
= "\\_SB.PCI0.GPI1",
93 .num_reset_vals
= ARRAY_SIZE(rst_map
),
94 .groups
= ptl_community1_groups
,
95 .num_groups
= ARRAY_SIZE(ptl_community1_groups
),
97 [COMM_3
] = { /* GPP: CPUJTAG, H, A, VGPIO3 */
99 .first_pad
= COM3_GRP_PAD_START
,
100 .last_pad
= COM3_GRP_PAD_END
,
101 .num_gpi_regs
= NUM_GPIO_COM3_GPI_REGS
,
102 .pad_cfg_base
= PAD_CFG_BASE
,
103 .pad_cfg_lock_offset
= PAD_CFG_LOCK_REG_0
,
104 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
105 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
106 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
107 .gpi_gpe_sts_reg_0
= GPI_GPE_STS_0
,
108 .gpi_gpe_en_reg_0
= GPI_GPE_EN_0
,
109 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
110 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
111 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
112 .name
= "GPP_CPUJTAG_H_A_VGPIO3",
113 .acpi_path
= "\\_SB.PCI0.GPI3",
114 .reset_map
= rst_map
,
115 .num_reset_vals
= ARRAY_SIZE(rst_map
),
116 .groups
= ptl_community3_groups
,
117 .num_groups
= ARRAY_SIZE(ptl_community3_groups
),
119 [COMM_4
] = { /* GPP: S */
120 .port
= PID_GPIOCOM4
,
121 .first_pad
= COM4_GRP_PAD_START
,
122 .last_pad
= COM4_GRP_PAD_END
,
123 .num_gpi_regs
= NUM_GPIO_COM4_GPI_REGS
,
124 .pad_cfg_base
= PAD_CFG_BASE
,
125 .pad_cfg_lock_offset
= PAD_CFG_LOCK_REG_0
,
126 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
127 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
128 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
129 .gpi_gpe_sts_reg_0
= GPI_GPE_STS_0
,
130 .gpi_gpe_en_reg_0
= GPI_GPE_EN_0
,
131 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
132 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
133 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
135 .acpi_path
= "\\_SB.PCI0.GPI4",
136 .reset_map
= rst_map
,
137 .num_reset_vals
= ARRAY_SIZE(rst_map
),
138 .groups
= ptl_community4_groups
,
139 .num_groups
= ARRAY_SIZE(ptl_community4_groups
),
141 [COMM_5
] = { /* GPP: B, D, VGPIO */
142 .port
= PID_GPIOCOM5
,
143 .first_pad
= COM5_GRP_PAD_START
,
144 .last_pad
= COM5_GRP_PAD_END
,
145 .num_gpi_regs
= NUM_GPIO_COM5_GPI_REGS
,
146 .pad_cfg_base
= PAD_CFG_BASE
,
147 .pad_cfg_lock_offset
= PAD_CFG_LOCK_REG_0
,
148 .host_own_reg_0
= HOSTSW_OWN_REG_0
,
149 .gpi_int_sts_reg_0
= GPI_INT_STS_0
,
150 .gpi_int_en_reg_0
= GPI_INT_EN_0
,
151 .gpi_gpe_sts_reg_0
= GPI_GPE_STS_0
,
152 .gpi_gpe_en_reg_0
= GPI_GPE_EN_0
,
153 .gpi_smi_sts_reg_0
= GPI_SMI_STS_0
,
154 .gpi_smi_en_reg_0
= GPI_SMI_EN_0
,
155 .max_pads_per_group
= GPIO_MAX_NUM_PER_GROUP
,
156 .name
= "GPP_B_D_VGPIO",
157 .acpi_path
= "\\_SB.PCI0.GPI5",
158 .reset_map
= rst_map
,
159 .num_reset_vals
= ARRAY_SIZE(rst_map
),
160 .groups
= ptl_community5_groups
,
161 .num_groups
= ARRAY_SIZE(ptl_community5_groups
),
165 const struct pad_community
*soc_gpio_get_community(size_t *num_communities
)
167 *num_communities
= ARRAY_SIZE(ptl_communities
);
168 return ptl_communities
;
171 const struct pmc_to_gpio_route
*soc_pmc_gpio_routes(size_t *num
)
173 static const struct pmc_to_gpio_route routes
[] = {
174 { PMC_GPP_V
, GPP_V
},
175 { PMC_GPP_C
, GPP_C
},
176 { PMC_GPP_F
, GPP_F
},
177 { PMC_GPP_E
, GPP_E
},
178 { PMC_GPP_A
, GPP_A
},
179 { PMC_GPP_H
, GPP_H
},
180 { PMC_GPP_VGPIO
, GPP_VGPIO
},
181 { PMC_GPP_B
, GPP_B
},
182 { PMC_GPP_D
, GPP_D
},
183 { PMC_GPP_S
, GPP_S
},
185 *num
= ARRAY_SIZE(routes
);