src/soc/intel/pantherlake/pcie_rp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <intelblocks/pcie_rp.h>
   4 #include <soc/pci_devs.h>
   5 #include <soc/pcie.h>
   6
   7 /*
   8  * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe
   9  * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's
  10  * PCIe remapping logic can return correct index (0-based)
  11  */
  12
  13 static const struct pcie_rp_group tbt_rp_groups[] = {
  14         { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 },
  15         { 0 }
  16 };
  17
  18 static const struct pcie_rp_group ptl_rp_groups[] = {
  19         { .slot = PCI_DEV_SLOT_PCIE_1,  .count = 8, .lcap_port_base = 1 },
  20 #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
  21         { .slot = PCI_DEV_SLOT_PCIE_2,  .count = 4, .lcap_port_base = 1 },
  22 #else
  23         { .slot = PCI_DEV_SLOT_PCIE_2, .count = 2, .lcap_port_base = 1 },
  24 #endif
  25         { 0 }
  26 };
  27
  28 const struct pcie_rp_group *get_pcie_rp_table(void)
  29 {
  30         return ptl_rp_groups;
  31 }
  32
  33 const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
  34 {
  35         return tbt_rp_groups;
  36 }
  37
  38 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
  39 {
  40         return PCIE_RP_PCH;
  41 }
  42
  43 int soc_get_cpu_rp_vw_idx(const struct device *dev)
  44 {
  45         return -1;
  46 }