src/soc/intel/pantherlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/ioapic.h>
   4 #include <console/console.h>
   5 #include <cpu/x86/msr.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <intelblocks/cpulib.h>
   9 #include <intelblocks/msr.h>
  10 #include <intelblocks/power_limit.h>
  11 #include <intelblocks/systemagent.h>
  12 #include <soc/iomap.h>
  13 #include <soc/soc_chip.h>
  14 #include <soc/systemagent.h>
  15 #include <static.h>
  16
  17 /*
  18  * SoC implementation
  19  *
  20  * Add all known fixed memory ranges for Host Controller/Memory
  21  * controller.
  22  */
  23 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  24 {
  25         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  26                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  27                 { SAFBAR, SAF_BASE_ADDRESS, SAF_BASE_SIZE, "SAFBAR" },
  28                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  29                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  30                 /* First field (sa_mmio_descriptor.index) is not used, setting to 0: */
  31                 { 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" },
  32                 { 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" },
  33                 { 0, IO_APIC_ADDR, APIC_SIZE, "APIC" },
  34                 { 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" },
  35         };
  36
  37         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  38                         ARRAY_SIZE(soc_fixed_resources));
  39
  40         /* Add Vt-d resources if VT-d is enabled */
  41         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  42                 return;
  43
  44         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  45                         ARRAY_SIZE(soc_vtd_resources));
  46 }
  47
  48 /*
  49  * Set MMIO resource's fields
  50  */
  51 static void set_mmio_resource(
  52         struct sa_mmio_descriptor *resource,
  53         uint64_t base,
  54         uint64_t size,
  55         const char *description)
  56 {
  57         if (resource == NULL) {
  58                 printk(BIOS_ERR, "%s: argument resource is NULL for %s\n",
  59                 __func__, description);
  60                 return;
  61         }
  62         resource->base = base;
  63         resource->size = size;
  64         resource->description = description;
  65 }
  66
  67 int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
  68         uint64_t *prmrr_mask)
  69 {
  70         msr_t msr;
  71         msr = rdmsr(MSR_PRMRR_BASE_0);
  72         *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
  73         msr = rdmsr(MSR_PRMRR_PHYS_MASK);
  74         *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
  75         return 0;
  76 }
  77
  78 /*
  79  * SoC implementation
  80  *
  81  * Add all known configurable memory ranges for Host Controller/Memory
  82  * controller.
  83  */
  84 void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
  85 {
  86         uint64_t size, base, tseg_base;
  87         int count = 0;
  88         struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */
  89
  90         /* MMCONF */
  91         size = sa_get_mmcfg_size();
  92         if (size > 0)
  93                 set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS,
  94                         size, "MMCONF");
  95
  96         /* DSM */
  97         size = sa_get_dsm_size();
  98         if (size > 0) {
  99                 base = pci_read_config32(dev, BDSM) & 0xFFF00000;
 100                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
 101         }
 102
 103         /* TSEG */
 104         size = sa_get_tseg_size();
 105         tseg_base = sa_get_tseg_base();
 106         if (size > 0)
 107                 set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
 108
 109         /* PMRR */
 110         size = get_valid_prmrr_size();
 111         if (size > 0) {
 112                 uint64_t mask;
 113                 if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) {
 114                         base &= mask;
 115                         set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR");
 116                 } else {
 117                         printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n");
 118                 }
 119         }
 120
 121         /* GSM */
 122         size = sa_get_gsm_size();
 123         if (size > 0) {
 124                 base = sa_get_gsm_base();
 125                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM");
 126         }
 127
 128         /* DPR */
 129         size = sa_get_dpr_size();
 130         if (size > 0) {
 131                 /* DPR just below TSEG: */
 132                 base = tseg_base - size;
 133                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR");
 134         }
 135
 136         /* Add all the above */
 137         sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count);
 138 }
 139
 140 static void configure_tdp(struct device *dev)
 141 {
 142         struct soc_power_limits_config *soc_config;
 143         struct device *sa;
 144         uint16_t sa_pci_id;
 145         u8 tdp;
 146         size_t i;
 147         bool config_tdp = false;
 148         struct soc_intel_pantherlake_config *config;
 149
 150         config = config_of_soc();
 151
 152         /* Get System Agent PCI ID */
 153         sa = pcidev_path_on_root(PCI_DEVFN_ROOT);
 154         sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
 155
 156         if (sa_pci_id == 0xFFFF) {
 157                 printk(BIOS_WARNING, "Unknown SA PCI Device!\n");
 158                 return;
 159         }
 160
 161         tdp = get_cpu_tdp();
 162
 163         /*
 164          * Choose power limits configuration based on the CPU SA PCI ID and
 165          * CPU TDP value.
 166          */
 167         for (i = 0; i < ARRAY_SIZE(cpuid_to_ptl); i++) {
 168                 if (sa_pci_id == cpuid_to_ptl[i].cpu_id &&
 169                                 tdp == cpuid_to_ptl[i].cpu_tdp) {
 170                         soc_config = &config->power_limits_config[cpuid_to_ptl[i].limits];
 171                         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 172                         config_tdp = true;
 173                         printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n",
 174                                 sa_pci_id);
 175                         break;
 176                 }
 177         }
 178
 179         if (!config_tdp) {
 180                 printk(BIOS_WARNING, "Skipped power limits configuration for SA PCI ID: 0x%4x\n",
 181                         sa_pci_id);
 182                 return;
 183         }
 184 }
 185
 186 /*
 187  * SoC implementation
 188  *
 189  * Perform System Agent Initialization during ramstage phase.
 190  */
 191 void soc_systemagent_init(struct device *dev)
 192 {
 193         /* Enable Power Aware Interrupt Routing */
 194         enable_power_aware_intr();
 195
 196         /* Configure TDP */
 197         configure_tdp(dev);
 198 }
 199
 200 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
 201 {
 202         switch (capid0_a_ddrsz) {
 203         case 1:
 204                 return 8192;
 205         case 2:
 206                 return 4096;
 207         case 3:
 208                 return 2048;
 209         default:
 210                 return 65536;
 211         }
 212 }