1 ## SPDX-License-Identifier: GPL-2.0-only
3 ifeq ($(CONFIG_SOC_QC_IPQ40XX
),y
)
7 bootblock-
$(CONFIG_SPI_FLASH
) += spi.c
21 romstage-y
+= blobs_init.c
23 romstage-
$(CONFIG_SPI_FLASH
) += spi.c
31 ramstage-y
+= blobs_init.c
36 ramstage-
$(CONFIG_SPI_FLASH
) += spi.c
38 ramstage-y
+= uart.c
# Want the UART always ready for the kernels' earlyprintk
40 ramstage-y
+= tz_wrapper.S
47 ifeq ($(CONFIG_USE_BLOBS
),y
)
49 $(objcbfs
)/bootblock.bin
: $(call strip_quotes
,$(CONFIG_SBL_ELF
)) \
50 $(objcbfs
)/bootblock.elf
51 @printf
" CRXBL $(subst $(obj)/,,$(^)) $(subst $(obj)/,,$(@))\n"
52 @
$(CONFIG_SBL_UTIL_PATH
)/createxbl.py
-f
$(CONFIG_SBL_ELF
) \
53 -s
$(objcbfs
)/bootblock.elf
-o
$@
-a
32 -b
32
57 CPPFLAGS_common
+= -Isrc
/soc
/qualcomm
/ipq40xx
/include
59 # List of binary blobs coreboot needs in CBFS to be able to boot up this SOC
60 mbn-files
:= $(CONFIG_CDT_MBN
) $(CONFIG_DDR_MBN
) $(CONFIG_TZ_MBN
)
62 # Location of the binary blobs
63 mbn-root
:= 3rdparty
/blobs
/cpu
/qualcomm
/ipq40xx
65 # Create make variables to aid cbfs-files-handler in processing the blobs (add
66 # them all as raw binaries at the root level).
67 $(foreach f
,$(mbn-files
),$(eval cbfs-files-y
+= $(f
))\
68 $(eval
$(f
)-file
:= $(mbn-root
)/$(f
))\
69 $(eval
$(f
)-type
:= raw
))