ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
[coreboot.git] / src / soc / ti / am335x / gpio.c
blobd3d3581f860a796b0d44bddc1640a7ecfd345698
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <soc/ti/am335x/gpio.h>
6 #include <stdint.h>
8 static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned int gpio,
9 uint32_t *bit)
11 unsigned int bank = gpio / AM335X_GPIO_BITS_PER_BANK;
13 if (bank >= ARRAY_SIZE(am335x_gpio_banks)) {
14 printk(BIOS_ERR, "Bad gpio index %d.\n", gpio);
15 return NULL;
17 *bit = 1 << (gpio % 32);
18 return am335x_gpio_banks[bank];
21 void am335x_disable_gpio_irqs(void)
23 int i;
25 for (i = 0; i < ARRAY_SIZE(am335x_gpio_banks); i++)
26 write32(&am335x_gpio_banks[i]->irqstatus_clr_0, 0xffffffff);
29 int gpio_direction_input(unsigned int gpio)
31 uint32_t bit;
32 struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
34 if (!regs)
35 return -1;
36 setbits32(&regs->oe, bit);
37 return 0;
40 int gpio_direction_output(unsigned int gpio, int value)
42 uint32_t bit;
43 struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
45 if (!regs)
46 return -1;
47 if (value)
48 write32(&regs->setdataout, bit);
49 else
50 write32(&regs->cleardataout, bit);
51 clrbits32(&regs->oe, bit);
52 return 0;
55 int gpio_get_value(unsigned int gpio)
57 uint32_t bit;
58 struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
60 if (!regs)
61 return -1;
62 return (read32(&regs->datain) & bit) ? 1 : 0;
65 int gpio_set_value(unsigned int gpio, int value)
67 uint32_t bit;
68 struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
70 if (!regs)
71 return -1;
72 if (value)
73 write32(&regs->setdataout, bit);
74 else
75 write32(&regs->cleardataout, bit);
76 return 0;