src/southbridge/intel/i82371eb/fadt.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * Based on src/southbridge/via/vt8237r/vt8237_fadt.c
   5  */
   6
   7 #include <acpi/acpi.h>
   8 #include <device/device.h>
   9 #include <device/pci.h>
  10
  11 #include "i82371eb.h"
  12
  13 /**
  14  * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
  15  * Reference: ACPIspec40a, 5.2.9, page 118
  16  */
  17 void acpi_fill_fadt(acpi_fadt_t *fadt)
  18 {
  19         fadt->pm1a_evt_blk = DEFAULT_PMBASE;
  20         fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
  21
  22         fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
  23         fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
  24
  25         /* *_len define register width in bytes */
  26         fadt->pm1_evt_len = 4;
  27         fadt->pm1_cnt_len = 2;
  28         fadt->pm_tmr_len = 4;
  29         fadt->gpe0_blk_len = 4;
  30
  31         fill_fadt_extended_pm_io(fadt);
  32
  33         /*
  34          * bit  meaning
  35          * 0    1: We have user-visible legacy devices
  36          * 1    1: 8042
  37          * 2    0: VGA is ok to probe
  38          * 3    1: MSI are not supported
  39          */
  40         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042 |
  41                                ACPI_FADT_MSI_NOT_SUPPORTED;
  42         /*
  43          * bit  meaning
  44          * 0    WBINVD
  45          *      Processors in new ACPI-compatible systems are required to
  46          *      support this function and indicate this to OSPM by setting
  47          *      this field.
  48          * 1    WBINVD_FLUSH
  49          *      If set, indicates that the hardware flushes all caches on the
  50          *      WBINVD instruction and maintains memory coherency, but does
  51          *      not guarantee the caches are invalidated.
  52          * 2    PROC_C1
  53          *      C1 power state (x86 hlt instruction) is supported on all cpus
  54          * 3    P_LVL2_UP
  55          *      0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor
  56          * 4    PWR_BUTTON
  57          *      0: pwr button is fixed feature
  58          *      1: pwr button has control method device if present
  59          * 5    SLP_BUTTON
  60          *      0: sleep button is fixed feature
  61          *      1: sleep button has control method device if present
  62          * 6    FIX_RTC
  63          *      0: RTC wake status supported in fixed register spce
  64          * 7    RTC_S4
  65          *      1: RTC can wake from S4
  66          * 8    TMR_VAL_EXT
  67          *      1: pmtimer is 32bit, 0: pmtimer is 24bit
  68          * 9    DCK_CAP
  69          *      1: system supports docking station
  70          * 10   RESET_REG_SUPPORT
  71          *      1: fadt describes reset register for system reset
  72          * 11   SEALED_CASE
  73          *      1: No expansion possible, sealed case
  74          * 12   HEADLESS
  75          *      1: Video output, keyboard and mouse are not connected
  76          * 13   CPU_SW_SLP
  77          *      1: Special processor instruction needs to be executed
  78          *      after writing SLP_TYP
  79          * 14   PCI_EXP_WAK
  80          *      1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set
  81          *      on platforms with pci express support
  82          * 15   USE_PLATFORM_CLOCK
  83          *      1: OS should prefer platform clock over processor internal
  84          *      clock.
  85          * 16   S4_RTC_STS_VALID
  86          * 17   REMOTE_POWER_ON_CAPABLE
  87          *      1: platform correctly supports OSPM leaving GPE wake events
  88          *      armed prior to an S5 transition.
  89          * 18   FORCE_APIC_CLUSTER_MODEL
  90          * 19   FORCE_APIC_PHYSICAL_DESTINATION_MODE
  91          */
  92         fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
  93                        ACPI_FADT_S4_RTC_WAKE;
  94 }