src/southbridge/intel/i82801ix/azalia.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/pci_ops.h>
   8 #include <device/mmio.h>
   9 #include <device/azalia_device.h>
  10 #include <types.h>
  11
  12 #include "chip.h"
  13 #include "i82801ix.h"
  14
  15 static int codec_detect(u8 *base)
  16 {
  17         u32 reg32;
  18
  19         if (azalia_enter_reset(base) != CB_SUCCESS)
  20                 goto no_codec;
  21
  22         if (azalia_exit_reset(base) != CB_SUCCESS)
  23                 goto no_codec;
  24
  25         /* Read in Codec location (BAR + 0xe)[2..0] */
  26         reg32 = read32(base + HDA_STATESTS_REG);
  27         reg32 &= 0x0f;
  28         if (!reg32)
  29                 goto no_codec;
  30
  31         return reg32;
  32
  33 no_codec:
  34         /* Codec not found, put HDA back in reset */
  35         azalia_enter_reset(base);
  36         printk(BIOS_DEBUG, "Azalia: No codec!\n");
  37         return 0;
  38 }
  39
  40 static void azalia_init(struct device *dev)
  41 {
  42         u8 *base;
  43         struct resource *res;
  44         u32 codec_mask;
  45
  46         // ESD
  47         pci_update_config32(dev, 0x134, ~0x00ff0000, 2 << 16);
  48
  49         // Link1 description
  50         pci_update_config32(dev, 0x140, ~0x00ff0000, 2 << 16);
  51
  52         // Port VC0 Resource Control Register
  53         pci_update_config32(dev, 0x114, ~0x000000ff, 1);
  54
  55         // VCi traffic class
  56         pci_or_config8(dev, 0x44, 7 << 0); // TC7
  57
  58         // VCi Resource Control
  59         pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */
  60
  61         /* Set Bus Master */
  62         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
  63
  64         // Docking not supported
  65         pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
  66
  67         /* Lock some R/WO bits by writing their current value. */
  68         pci_update_config32(dev, 0x74, ~0, 0);
  69
  70         res = probe_resource(dev, PCI_BASE_ADDRESS_0);
  71         if (!res)
  72                 return;
  73
  74         // NOTE this will break as soon as the Azalia gets a bar above 4G.
  75         // Is there anything we can do about it?
  76         base = res2mmio(res, 0, 0);
  77         printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
  78         codec_mask = codec_detect(base);
  79
  80         if (codec_mask) {
  81                 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
  82                 azalia_codecs_init(base, codec_mask);
  83         }
  84 }
  85
  86 static struct device_operations azalia_ops = {
  87         .read_resources         = pci_dev_read_resources,
  88         .set_resources          = pci_dev_set_resources,
  89         .enable_resources       = pci_dev_enable_resources,
  90         .init                   = azalia_init,
  91         .ops_pci                = &pci_dev_ops_pci,
  92 };
  93
  94 /* ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M */
  95 static const struct pci_driver i82801ix_azalia __pci_driver = {
  96         .ops    = &azalia_ops,
  97         .vendor = PCI_VID_INTEL,
  98         .device = PCI_DID_INTEL_82801IB_HD_AUDIO,
  99 };