spd/lp5: Add Hynix memory part
[coreboot.git] / src / southbridge / intel / i82801ix / smihandler.c
blobb5676ffb9aa25367f2b8e01a7c1849d2bd088785
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <types.h>
4 #include <console/console.h>
5 #include <cpu/x86/smm.h>
6 #include <device/pci_def.h>
7 #include <southbridge/intel/common/pmutil.h>
8 #include "i82801ix.h"
10 #include <soc/nvs.h>
12 void southbridge_smi_monitor(void)
14 #define IOTRAP(x) (trap_sts & (1 << x))
15 u32 trap_sts, trap_cycle;
16 u32 data, mask = 0;
17 int i;
19 trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
20 RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
22 trap_cycle = RCBA32(0x1e10);
23 for (i=16; i<20; i++) {
24 if (trap_cycle & (1 << i))
25 mask |= (0xff << ((i - 16) << 3));
28 /* IOTRAP(3) SMI function call */
29 if (IOTRAP(3)) {
30 if (gnvs && gnvs->smif)
31 io_trap_handler(gnvs->smif); // call function smif
32 return;
35 /* IOTRAP(2) currently unused
36 * IOTRAP(1) currently unused */
38 /* IOTRAP(0) SMIC */
39 if (IOTRAP(0)) {
40 if (!(trap_cycle & (1 << 24))) { // It's a write
41 printk(BIOS_DEBUG, "SMI1 command\n");
42 data = RCBA32(0x1e18);
44 // Fall through to debug
47 printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
48 for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
49 printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
50 printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
51 printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
53 if (!(trap_cycle & (1 << 24))) {
54 /* Write Cycle */
55 data = RCBA32(0x1e18);
56 printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
58 #undef IOTRAP
61 void southbridge_finalize_all(void)