util/autoport/haswell.go

   1 package main
   2
   3 import "fmt"
   4
   5 type haswellmc struct {
   6         variant string
   7 }
   8
   9 func divceil(a uint32, b uint32) uint32 {
  10         return (a + b - 1) / b
  11 }
  12
  13 func getPanelCfg(inteltool InteltoolData, isULT bool) string {
  14         var refclk uint32
  15         var pwm_hz uint32
  16
  17         if isULT {
  18                 refclk = 24000000
  19         } else {
  20                 refclk = 135000000
  21         }
  22         if (inteltool.IGD[0xc8254] >> 16) != 0 {
  23                 pwm_hz = refclk / 128 / (inteltool.IGD[0xc8254] >> 16)
  24         } else {
  25                 pwm_hz = 0
  26         }
  27
  28         gpu_panel_power_up_delay := (inteltool.IGD[0xc7208] >> 16) & 0x1fff
  29         gpu_panel_power_backlight_on_delay := inteltool.IGD[0xc7208] & 0x1fff
  30         gpu_panel_power_down_delay := (inteltool.IGD[0xc720c] >> 16) & 0x1fff
  31         gpu_panel_power_backlight_off_delay := inteltool.IGD[0xc720c] & 0x1fff
  32         gpu_panel_power_cycle_delay := inteltool.IGD[0xc7210] & 0x1f
  33
  34         return fmt.Sprintf(`{
  35                 .up_delay_ms            = %3d,
  36                 .down_delay_ms          = %3d,
  37                 .cycle_delay_ms         = %3d,
  38                 .backlight_on_delay_ms  = %3d,
  39                 .backlight_off_delay_ms = %3d,
  40                 .backlight_pwm_hz       = %3d,
  41         }`,
  42                 divceil(gpu_panel_power_up_delay, 10),
  43                 divceil(gpu_panel_power_down_delay, 10),
  44                 (gpu_panel_power_cycle_delay-1)*100,
  45                 divceil(gpu_panel_power_backlight_on_delay, 10),
  46                 divceil(gpu_panel_power_backlight_off_delay, 10),
  47                 pwm_hz)
  48 }
  49
  50 func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
  51         inteltool := ctx.InfoSource.GetInteltool()
  52
  53         isULT := (i.variant == "ULT")
  54         DevTree = DevTreeNode{
  55                 Chip:          "northbridge/intel/haswell",
  56                 MissingParent: "northbridge",
  57                 Comment:       "FIXME: check ec_present, usb_xhci_on_resume, gfx",
  58                 Registers: map[string]string{
  59                         "gpu_dp_b_hotplug":    FormatInt32((inteltool.IGD[0xc4030] >> 2) & 4),
  60                         "gpu_dp_c_hotplug":    FormatInt32((inteltool.IGD[0xc4030] >> 10) & 4),
  61                         "gpu_dp_d_hotplug":    FormatInt32((inteltool.IGD[0xc4030] >> 18) & 4),
  62                         "panel_cfg":           getPanelCfg(inteltool, isULT),
  63                         "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
  64                         "ec_present":          "false",
  65                         "usb_xhci_on_resume":  "false",
  66                         /* FIXME:XX hardcoded.  */
  67                         "gfx": "GMA_STATIC_DISPLAYS(0)",
  68                         "spd_addresses": "{0x50, 0x51, 0x52, 0x53}\" # FIXME: Put proper SPD map here",
  69                 },
  70                 Children: []DevTreeNode{
  71                         {
  72                                 Chip: "cpu/intel/haswell",
  73                                 Children: []DevTreeNode{
  74                                         {
  75                                                 Chip: "cpu_cluster",
  76                                                 Dev:  0,
  77                                                 Ops:  "haswell_cpu_bus_ops",
  78                                         },
  79                                 },
  80                         },
  81
  82                         {
  83                                 Chip:          "domain",
  84                                 Dev:           0,
  85                                 Ops:           "haswell_pci_domain_ops",
  86                                 PCIController: true,
  87                                 ChildPCIBus:   0,
  88                                 PCISlots: []PCISlot{
  89                                         PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: i.variant},
  90                                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: !isULT, additionalComment: "PCIe Bridge for discrete graphics"},
  91                                         PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
  92                                         PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
  93                                 },
  94                         },
  95                 },
  96         }
  97
  98         if isULT {
  99                 DevTree.Registers["dq_pins_interleaved"] = FormatBool(((inteltool.MCHBAR[0x2008] >> 10) & 1) == 0)
 100         }
 101
 102         PutPCIDev(addr, "Host bridge")
 103
 104         KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
 105         KconfigBool["HAVE_ACPI_TABLES"] = true
 106         KconfigBool["HAVE_ACPI_RESUME"] = true
 107
 108         DSDTIncludes = append(DSDTIncludes, DSDTInclude{
 109                 File: "cpu/intel/common/acpi/cpu.asl",
 110         })
 111
 112         DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
 113                 File: "northbridge/intel/haswell/acpi/hostbridge.asl",
 114         }, DSDTInclude{
 115                 File:    "drivers/intel/gma/acpi/default_brightness_levels.asl",
 116                 Comment: "FIXME: remove this if the board doesn't have backlight",
 117         })
 118 }
 119
 120 func init() {
 121         RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
 122         RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
 123         RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
 124         RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
 125         RegisterPCI(0x8086, 0x0d00, haswellmc{variant: "Crystal Well Desktop"})
 126         RegisterPCI(0x8086, 0x0d04, haswellmc{variant: "Crystal Well Mobile"})
 127         RegisterPCI(0x8086, 0x0d08, haswellmc{variant: "Crystal Well Server"})
 128         for _, id := range []uint16{
 129                 0x0402, 0x0412, 0x041e, 0x0422, 0x0d22, /* Desktop */
 130                 0x0406, 0x0416, 0x0426, /* Mobile */
 131                 0x040a, 0x041a, 0x042a, /* Server */
 132                 0x0a06, 0x0a16, 0x0a26, /* ULT */
 133                 0x0a0e, 0x0a1e, /* ULX */
 134                 0x0d16, 0x0d26, 0x0d36, /* Mobile 4+3, GT3e */
 135         } {
 136                 RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
 137         }
 138         /* CPU HD Audio */
 139         RegisterPCI(0x8086, 0x0a0c, GenericPCI{})
 140         RegisterPCI(0x8086, 0x0c0c, GenericPCI{})
 141 }