src/mainboard/prodrive/hermes/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpigen.h>
   4 #include <arch/cpu.h>
   5 #include <bootstate.h>
   6 #include <cbmem.h>
   7 #include <console/console.h>
   8 #include <crc_byte.h>
   9 #include <device/device.h>
  10 #include <device/dram/spd.h>
  11 #include <drivers/intel/gma/opregion.h>
  12 #include <gpio.h>
  13 #include <intelblocks/gpio.h>
  14 #include <intelblocks/pmclib.h>
  15 #include <smbios.h>
  16 #include <soc/gpio.h>
  17 #include <soc/pm.h>
  18 #include <string.h>
  19 #include <types.h>
  20
  21 #include "eeprom.h"
  22 #include "gpio.h"
  23
  24 const char *mainboard_vbt_filename(void)
  25 {
  26         const struct eeprom_bmc_settings *bmc_cfg = get_bmc_settings();
  27
  28         if (bmc_cfg && bmc_cfg->efp3_displayport)
  29                 return "vbt-avalanche.bin";
  30         else
  31                 return "vbt.bin"; /* Poseidon */
  32 }
  33
  34 /* FIXME: Example code below */
  35
  36 static void mb_configure_dp1_pwr(bool enable)
  37 {
  38         gpio_output(GPP_K3, enable);
  39 }
  40
  41 static void mb_configure_dp2_pwr(bool enable)
  42 {
  43         gpio_output(GPP_K4, enable);
  44 }
  45
  46 static void mb_configure_dp3_pwr(bool enable)
  47 {
  48         gpio_output(GPP_K5, enable);
  49 }
  50
  51 static void mb_hda_amp_enable(bool enable)
  52 {
  53         gpio_output(GPP_C19, enable);
  54 }
  55
  56 static void mb_usb31_rp1_pwr_enable(bool enable)
  57 {
  58         gpio_output(GPP_G0, enable);
  59 }
  60
  61 static void mb_usb31_rp2_pwr_enable(bool enable)
  62 {
  63         gpio_output(GPP_G1, enable);
  64 }
  65
  66 static void mb_usb31_fp_pwr_enable(bool enable)
  67 {
  68         gpio_output(GPP_G2, enable);
  69 }
  70
  71 static void mb_usb2_fp1_pwr_enable(bool enable)
  72 {
  73         gpio_output(GPP_G3, enable);
  74 }
  75
  76 static void mb_usb2_fp2_pwr_enable(bool enable)
  77 {
  78         gpio_output(GPP_G4, enable);
  79 }
  80
  81 static void copy_meminfo(const struct dimm_info *dimm, union eeprom_dimm_layout *l)
  82 {
  83         memset(l, 0, sizeof(*l));
  84         if (dimm->dimm_size == 0)
  85                 return;
  86
  87         strncpy(l->name, (char *)dimm->module_part_number, sizeof(l->name) - 1);
  88         l->capacity_mib = dimm->dimm_size;
  89         l->data_width_bits = 8 * (1 << (dimm->bus_width & 0x7));
  90         l->bus_width_bits = l->data_width_bits + 8 * ((dimm->bus_width >> 3) & 0x3);
  91         l->ranks = dimm->rank_per_dimm;
  92         l->controller_id = 0;
  93         strncpy(l->manufacturer, spd_manufacturer_name(dimm->mod_id),
  94                 sizeof(l->manufacturer) - 1);
  95 }
  96
  97 /*
  98  * Collect board specific settings and update the CFG EEPROM if necessary.
  99  * This allows the BMC webui to display the current hardware configuration.
 100  */
 101 static void update_board_layout(void)
 102 {
 103         struct eeprom_board_layout layout = {0};
 104
 105         printk(BIOS_INFO, "MB: Collecting Board Layout information\n");
 106
 107         /* Update CPU fields */
 108         for (struct device *cpu = all_devices; cpu; cpu = cpu->next) {
 109                 if (!is_enabled_cpu(cpu))
 110                         continue;
 111                 layout.cpu_count++;
 112                 if (!layout.cpu_name[0])
 113                         strcpy(layout.cpu_name, cpu->name);
 114         }
 115
 116         if (cpuid_get_max_func() >= 0x16)
 117                 layout.cpu_max_non_turbo_frequency = cpuid_eax(0x16);
 118
 119         /* PCH */
 120         strcpy(layout.pch_name, "Cannonlake-H C246");
 121
 122         /* DRAM */
 123         struct memory_info *meminfo = cbmem_find(CBMEM_ID_MEMINFO);
 124         if (meminfo) {
 125                 const size_t meminfo_max = MIN(meminfo->dimm_cnt, ARRAY_SIZE(meminfo->dimm));
 126                 for (size_t i = 0; i < MIN(meminfo_max, ARRAY_SIZE(layout.dimm)); i++)
 127                         copy_meminfo(&meminfo->dimm[i], &layout.dimm[i]);
 128         }
 129
 130         /* Update CRC */
 131         layout.signature = CRC(layout.raw_layout, sizeof(layout.raw_layout), crc32_byte);
 132
 133         printk(BIOS_DEBUG, "BOARD LAYOUT:\n");
 134         printk(BIOS_DEBUG, " Signature : 0x%x\n", layout.signature);
 135         printk(BIOS_DEBUG, " CPU name  : %s\n", layout.cpu_name);
 136         printk(BIOS_DEBUG, " CPU count : %u\n", layout.cpu_count);
 137         printk(BIOS_DEBUG, " CPU freq  : %u\n", layout.cpu_max_non_turbo_frequency);
 138         printk(BIOS_DEBUG, " PCH name  : %s\n", layout.pch_name);
 139         for (size_t i = 0; i < ARRAY_SIZE(layout.dimm); i++)
 140                 printk(BIOS_DEBUG, " DRAM SIZE : %u\n", layout.dimm[i].capacity_mib);
 141
 142         if (write_board_settings(&layout))
 143                 printk(BIOS_ERR, "MB: Failed to update Board Layout\n");
 144 }
 145
 146 static void mainboard_init(void *chip_info)
 147 {
 148         const struct eeprom_board_settings *const board_cfg = get_board_settings();
 149
 150         if (!board_cfg)
 151                 return;
 152
 153         /* Enable internal speaker amplifier */
 154         if (board_cfg->front_panel_audio == 2)
 155                 mb_hda_amp_enable(1);
 156         else
 157                 mb_hda_amp_enable(0);
 158 }
 159
 160 static void mainboard_final(struct device *dev)
 161 {
 162         update_board_layout();
 163
 164         const struct eeprom_board_settings *const board_cfg = get_board_settings();
 165
 166         if (!board_cfg)
 167                 return;
 168
 169         /* Encoding: 0 -> S0, 1 -> S5 */
 170         const bool on = !board_cfg->power_state_after_g3;
 171
 172         pmc_soc_set_afterg3_en(on);
 173 }
 174
 175 static const char *format_pn(const char *prefix, size_t offset)
 176 {
 177         static char buffer[32 + HERMES_SN_PN_LENGTH] = { 0 };
 178
 179         const char *part_num = eeprom_read_serial(offset, "N/A");
 180
 181         snprintf(buffer, sizeof(buffer), "%s%s", prefix, part_num);
 182
 183         return buffer;
 184 }
 185
 186 static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
 187 {
 188         const size_t board_offset = offsetof(struct eeprom_layout, board_part_number);
 189         const size_t product_offset = offsetof(struct eeprom_layout, product_part_number);
 190         t->count = smbios_add_string(t->eos, format_pn("Board P/N: ", board_offset));
 191         t->count = smbios_add_string(t->eos, format_pn("Product P/N: ", product_offset));
 192 }
 193
 194 #if CONFIG(HAVE_ACPI_TABLES)
 195 static void mainboard_acpi_fill_ssdt(const struct device *dev)
 196 {
 197         const struct eeprom_board_settings *const board_cfg = get_board_settings();
 198
 199         if (!board_cfg)
 200                 return;
 201
 202         const unsigned int usb_power_gpios[] = { GPP_G0, GPP_G1, GPP_G2, GPP_G3, GPP_G4 };
 203
 204         /* Function pointer to write STXS or CTXS according to EEPROM board setting */
 205         int (*acpigen_write_soc_gpio_op)(unsigned int gpio_num);
 206
 207         if (board_cfg->usb_powered_in_s5)
 208                 acpigen_write_soc_gpio_op = acpigen_soc_set_tx_gpio;
 209         else
 210                 acpigen_write_soc_gpio_op = acpigen_soc_clear_tx_gpio;
 211
 212         acpigen_write_method("\\_SB.MPTS", 1);
 213         {
 214                 acpigen_write_if_lequal_op_int(ARG0_OP, 5);
 215                 {
 216                         for (size_t i = 0; i < ARRAY_SIZE(usb_power_gpios); i++)
 217                                 acpigen_write_soc_gpio_op(usb_power_gpios[i]);
 218                 }
 219                 acpigen_pop_len();
 220         }
 221         acpigen_pop_len();
 222 }
 223 #endif
 224
 225 static void mainboard_enable(struct device *dev)
 226 {
 227         /* FIXME: Do runtime configuration once the board is production ready */
 228         mb_configure_dp1_pwr(1);
 229         mb_configure_dp2_pwr(1);
 230         mb_configure_dp3_pwr(1);
 231
 232         mb_usb31_rp1_pwr_enable(1);
 233         mb_usb31_rp2_pwr_enable(1);
 234         mb_usb31_fp_pwr_enable(1);
 235         mb_usb2_fp1_pwr_enable(1);
 236         mb_usb2_fp2_pwr_enable(1);
 237
 238         dev->ops->final = mainboard_final;
 239         dev->ops->get_smbios_strings = mainboard_smbios_strings;
 240
 241 #if CONFIG(HAVE_ACPI_TABLES)
 242         dev->ops->acpi_fill_ssdt = mainboard_acpi_fill_ssdt;
 243 #endif
 244 }
 245
 246 struct chip_operations mainboard_ops = {
 247         .init       = mainboard_init,
 248         .enable_dev = mainboard_enable,
 249 };
 250
 251 static void log_reset_causes(void)
 252 {
 253         struct chipset_power_state *ps = pmc_get_power_state();
 254
 255         if (!ps) {
 256                 printk(BIOS_ERR, "chipset_power_state not found!\n");
 257                 return;
 258         }
 259
 260         union {
 261                 struct eeprom_reset_cause_regs regs;
 262                 uint8_t raw[sizeof(struct eeprom_reset_cause_regs)];
 263         } reset_cause = {
 264                 .regs = {
 265                         .gblrst_cause0 = ps->gblrst_cause[0],
 266                         .gblrst_cause1 = ps->gblrst_cause[1],
 267                         .hpr_cause0 = ps->hpr_cause0,
 268                 },
 269         };
 270
 271         const size_t base = offsetof(struct eeprom_layout, reset_cause_regs);
 272         for (size_t i = 0; i < ARRAY_SIZE(reset_cause.raw); i++)
 273                 eeprom_write_byte(reset_cause.raw[i], base + i);
 274 }
 275
 276 /* Must happen before MPinit */
 277 static void mainboard_early(void *unused)
 278 {
 279         const struct eeprom_board_settings *const board_cfg = get_board_settings();
 280         config_t *config = config_of_soc();
 281
 282         if (board_cfg) {
 283                 /* Set Deep Sx */
 284                 config->deep_s5_enable_ac = board_cfg->deep_sx_enabled;
 285                 config->deep_s5_enable_dc = board_cfg->deep_sx_enabled;
 286
 287                 config->disable_vmx = board_cfg->vtx_disabled;
 288         }
 289
 290         if (check_signature(offsetof(struct eeprom_layout, supd), FSPS_UPD_SIGNATURE)) {
 291                 struct {
 292                         struct {
 293                                 u8 TurboMode;
 294                         } FspsConfig;
 295                 } supd = {0};
 296
 297                 READ_EEPROM_FSP_S((&supd), FspsConfig.TurboMode);
 298                 config->cpu_turbo_disable = !supd.FspsConfig.TurboMode;
 299         }
 300
 301         log_reset_causes();
 302 }
 303
 304 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL);