src/southbridge/intel/i82801ix/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <device/pci_ops.h>
   5 #include <device/smbus_host.h>
   6 #include <southbridge/intel/common/pmutil.h>
   7 #include "i82801ix.h"
   8 #include "chip.h"
   9
  10 void i82801ix_lpc_setup(void)
  11 {
  12         const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
  13         const struct device *dev = pcidev_on_root(0x1f, 0);
  14         const struct southbridge_intel_i82801ix_config *config;
  15
  16         /* Configure serial IRQs.*/
  17         pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
  18         /*
  19          * Enable some common LPC IO ranges:
  20          * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
  21          * - 0x60/0x64, 0x62/0x66 often KBC/EC
  22          * - 0x3f0-0x3f5/0x3f7 FDD
  23          * - 0x378-0x37f and 0x778-0x77f LPT
  24          * - 0x2f8-0x2ff COMB
  25          * - 0x3f8-0x3ff COMA
  26          * - 0x208-0x20f GAMEH
  27          * - 0x200-0x207 GAMEL
  28          */
  29         pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
  30         pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
  31                            | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
  32                            | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
  33                            | COMB_LPC_EN | COMA_LPC_EN);
  34
  35         /* Set up generic decode ranges */
  36         if (!dev || !dev->chip_info)
  37                 return;
  38         config = dev->chip_info;
  39
  40         pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
  41         pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
  42         pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
  43         pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
  44 }
  45
  46 void i82801ix_early_init(void)
  47 {
  48         const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
  49
  50         if (ENV_RAMINIT)
  51                 enable_smbus();
  52
  53         /* Set up RCBA. */
  54         pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
  55
  56         /* Set up PMBASE. */
  57         pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
  58         /* Enable PMBASE. */
  59         pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80);
  60
  61         /* Set up GPIOBASE. */
  62         pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);
  63         /* Enable GPIO. */
  64         pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10);
  65
  66         /* Reset watchdog. */
  67         outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */
  68         outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */
  69
  70         /* Enable upper 128bytes of CMOS. */
  71         RCBA32(0x3400) = (1 << 2);
  72
  73         /* Initialize power management initialization
  74            register early as it affects reboot behavior. */
  75         /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6
  76            and 0xe (required if ME is disabled but present), bit 31 locks it.
  77            The other bits are 'must write'. */
  78         u8 reg8 = pci_read_config8(d31f0, 0xac);
  79
  80         /* FIXME: It's a 8-bit variable!!! */
  81         reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
  82         pci_write_config8(d31f0, 0xac, reg8);
  83
  84         /* TODO: If RTC power failed, reset RTC state machine
  85                  (set, then reset RTC 0x0b bit7) */
  86
  87         /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
  88                  before they get cleared. */
  89 }