src/southbridge/intel/lynxpoint/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H
   4 #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H
   5
   6 #include <stdint.h>
   7
   8 struct southbridge_intel_lynxpoint_config {
   9         /**
  10          * GPI Routing configuration for LynxPoint-H
  11          *
  12          * Only the lower two bits have a meaning:
  13          * 00: No effect
  14          * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  15          * 10: SCI (if corresponding GPIO_EN bit is also set)
  16          * 11: reserved
  17          */
  18         uint8_t gpi0_routing;
  19         uint8_t gpi1_routing;
  20         uint8_t gpi2_routing;
  21         uint8_t gpi3_routing;
  22         uint8_t gpi4_routing;
  23         uint8_t gpi5_routing;
  24         uint8_t gpi6_routing;
  25         uint8_t gpi7_routing;
  26         uint8_t gpi8_routing;
  27         uint8_t gpi9_routing;
  28         uint8_t gpi10_routing;
  29         uint8_t gpi11_routing;
  30         uint8_t gpi12_routing;
  31         uint8_t gpi13_routing;
  32         uint8_t gpi14_routing;
  33         uint8_t gpi15_routing;
  34
  35         uint32_t gpe0_en_1;
  36         uint32_t gpe0_en_2;
  37         uint32_t gpe0_en_3;
  38         uint32_t gpe0_en_4;
  39         uint32_t alt_gp_smi_en;
  40
  41         /* SATA configuration */
  42         uint8_t sata_port_map;
  43         uint32_t sata_port0_gen3_tx;
  44         uint32_t sata_port1_gen3_tx;
  45         uint32_t sata_port0_gen3_dtle;
  46         uint32_t sata_port1_gen3_dtle;
  47
  48         /*
  49          * SATA DEVSLP Mux
  50          * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
  51          * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
  52          */
  53         uint8_t sata_devslp_mux;
  54
  55         /*
  56          * DEVSLP Disable
  57          * 0: DEVSLP is enabled
  58          * 1: DEVSLP is disabled
  59          */
  60         uint8_t sata_devslp_disable;
  61
  62         uint32_t gen1_dec;
  63         uint32_t gen2_dec;
  64         uint32_t gen3_dec;
  65         uint32_t gen4_dec;
  66
  67         /* Enable linear PCIe Root Port function numbers starting at zero */
  68         bool pcie_port_coalesce;
  69
  70         /* Force root port ASPM configuration with port bitmap */
  71         uint8_t pcie_port_force_aspm;
  72
  73         /* Put SerialIO devices into ACPI mode instead of a PCI device */
  74         uint8_t sio_acpi_mode;
  75
  76         /* I2C voltage select: 0=3.3V 1=1.8V */
  77         uint8_t sio_i2c0_voltage;
  78         uint8_t sio_i2c1_voltage;
  79
  80         /*
  81          * Clock Disable Map:
  82          * [21:16] = CLKOUT_PCIE# 5-0
  83          *    [24] = CLKOUT_ITPXDP
  84          */
  85         uint32_t icc_clock_disable;
  86
  87         /* Route USB ports to XHCI per default */
  88         uint8_t xhci_default;
  89
  90         /* Information for the ACPI FADT. */
  91         bool docking_supported;
  92 };
  93
  94 #endif  /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */