src/southbridge/intel/lynxpoint/pcie.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <commonlib/helpers.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pciexp.h>
   9 #include <device/pci_ids.h>
  10 #include <device/pci_ops.h>
  11 #include "iobp.h"
  12 #include "pch.h"
  13 #include <southbridge/intel/common/gpio.h>
  14 #include <stdint.h>
  15 #include "chip.h"
  16
  17 #define MAX_NUM_ROOT_PORTS 8
  18
  19 struct root_port_config {
  20         /* RPFN is a write-once register so keep a copy until it is written */
  21         u32 orig_rpfn;
  22         u32 new_rpfn;
  23         u32 pin_ownership;
  24         u32 strpfusecfg1;
  25         u32 strpfusecfg2;
  26         u32 strpfusecfg3;
  27         u32 b0d28f0_32c;
  28         u32 b0d28f4_32c;
  29         u32 b0d28f5_32c;
  30         bool coalesce;
  31         int gbe_port;
  32         int num_ports;
  33         struct device *ports[MAX_NUM_ROOT_PORTS];
  34 };
  35
  36 static struct root_port_config rpc;
  37
  38 static inline int max_root_ports(void)
  39 {
  40         if (pch_is_lp() || pch_silicon_id() == PCI_DID_INTEL_LPT_H81)
  41                 return 6;
  42
  43         return 8;
  44 }
  45
  46 static inline int root_port_is_first(struct device *dev)
  47 {
  48         return PCI_FUNC(dev->path.pci.devfn) == 0;
  49 }
  50
  51 static inline int root_port_is_last(struct device *dev)
  52 {
  53         return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
  54 }
  55
  56 /* Root ports are numbered 1..N in the documentation. */
  57 static inline int root_port_number(struct device *dev)
  58 {
  59         return PCI_FUNC(dev->path.pci.devfn) + 1;
  60 }
  61
  62 static bool is_rp_enabled(int rp)
  63 {
  64         ASSERT(rp > 0 && rp <= ARRAY_SIZE(rpc.ports));
  65
  66         if (rpc.ports[rp - 1] == NULL)
  67                 return false;
  68
  69         return rpc.ports[rp - 1]->enabled;
  70 }
  71
  72 static void root_port_config_update_gbe_port(void)
  73 {
  74         /* Is the Gbe Port enabled? */
  75         if (!((rpc.strpfusecfg1 >> 19) & 1))
  76                 return;
  77
  78         if (pch_is_lp()) {
  79                 switch ((rpc.strpfusecfg1 >> 16) & 0x7) {
  80                 case 0:
  81                         rpc.gbe_port = 3;
  82                         break;
  83                 case 1:
  84                         rpc.gbe_port = 4;
  85                         break;
  86                 case 2:
  87                 case 3:
  88                 case 4:
  89                 case 5:
  90                         /* Lanes 0-4 of Root Port 5. */
  91                         rpc.gbe_port = 5;
  92                         break;
  93                 default:
  94                         printk(BIOS_DEBUG, "Invalid GbE Port Selection.\n");
  95                 }
  96         } else {
  97                 /* Non-LP has 1:1 mapping with root ports. */
  98                 rpc.gbe_port = ((rpc.strpfusecfg1 >> 16) & 0x7) + 1;
  99         }
 100 }
 101
 102 static void update_num_ports(void)
 103 {
 104         /*
 105          * According to existing code in 'root_port_check_disable()', which does
 106          * not agree with the confusing information on the datasheets, the last
 107          * visible function depends on the strapped root port width as follows:
 108          *
 109          * +-----+----+----+----+----+
 110          * | RPC | #5 | #6 | #7 | #8 |
 111          * +-----+----+----+----+----+
 112          * |  0  | x1 | x1 | x1 | x1 |
 113          * |  1  | x2 |    | x1 | x1 |
 114          * |  2  | x2 |    | x2 |    |
 115          * |  3  | x4 |    |    |    |
 116          * +-----+----+----+----+----+
 117          */
 118         switch ((rpc.strpfusecfg2 >> 14) & 0x3) {
 119         case 0:
 120         case 1:
 121                 break;
 122         case 2:
 123                 rpc.num_ports = MIN(rpc.num_ports, 7);
 124                 break;
 125         case 3:
 126                 rpc.num_ports = MIN(rpc.num_ports, 5);
 127                 break;
 128         }
 129
 130         printk(BIOS_DEBUG, "Adjusted number of PCIe root ports to %d as per strpfusecfg2\n",
 131                rpc.num_ports);
 132 }
 133
 134 static void root_port_init_config(struct device *dev)
 135 {
 136         int rp;
 137
 138         if (root_port_is_first(dev)) {
 139                 rpc.orig_rpfn = RCBA32(RPFN);
 140                 rpc.new_rpfn = rpc.orig_rpfn;
 141                 rpc.num_ports = max_root_ports();
 142                 rpc.gbe_port = -1;
 143
 144                 rpc.pin_ownership = pci_read_config32(dev, 0x410);
 145                 root_port_config_update_gbe_port();
 146
 147                 if (dev->chip_info != NULL) {
 148                         struct southbridge_intel_lynxpoint_config *config;
 149
 150                         config = dev->chip_info;
 151                         rpc.coalesce = config->pcie_port_coalesce;
 152                 }
 153         }
 154
 155         rp = root_port_number(dev);
 156         if (rp > rpc.num_ports) {
 157                 printk(BIOS_ERR, "Found Root Port %d, expecting %d\n",
 158                        rp, rpc.num_ports);
 159                 return;
 160         }
 161
 162         /* Read the fuse configuration and pin ownership. */
 163         switch (rp) {
 164         case 1:
 165                 rpc.strpfusecfg1 = pci_read_config32(dev, 0xfc);
 166                 rpc.b0d28f0_32c = pci_read_config32(dev, 0x32c);
 167                 break;
 168         case 5:
 169                 rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc);
 170                 rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c);
 171
 172                 if (!pch_is_lp())
 173                         update_num_ports();
 174
 175                 break;
 176         case 6:
 177                 rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c);
 178                 rpc.strpfusecfg3 = pci_read_config32(dev, 0xfc);
 179                 break;
 180         default:
 181                 break;
 182         }
 183
 184         /* Cache pci device. */
 185         rpc.ports[rp - 1] = dev;
 186 }
 187
 188 /* Update devicetree with new Root Port function number assignment */
 189 static void pch_pcie_device_set_func(int index, int pci_func)
 190 {
 191         struct device *dev;
 192         unsigned int new_devfn;
 193
 194         dev = rpc.ports[index];
 195
 196         /* Set the new PCI function field for this Root Port. */
 197         rpc.new_rpfn &= ~RPFN_FNMASK(index);
 198         rpc.new_rpfn |= RPFN_FNSET(index, pci_func);
 199
 200         /* Determine the new devfn for this port */
 201         new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, pci_func);
 202
 203         if (dev && dev->path.pci.devfn != new_devfn) {
 204                 printk(BIOS_DEBUG,
 205                        "PCH: PCIe map %02x.%1x -> %02x.%1x\n",
 206                        PCI_SLOT(dev->path.pci.devfn),
 207                        PCI_FUNC(dev->path.pci.devfn),
 208                        PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
 209
 210                 dev->path.pci.devfn = new_devfn;
 211         }
 212 }
 213
 214 static void pcie_enable_clock_gating(void)
 215 {
 216         int i;
 217         int is_lp;
 218         int enabled_ports;
 219
 220         is_lp = pch_is_lp();
 221         enabled_ports = 0;
 222
 223         for (i = 0; i < rpc.num_ports; i++) {
 224                 struct device *dev;
 225                 int rp;
 226
 227                 dev = rpc.ports[i];
 228                 if (!dev)
 229                         continue;
 230
 231                 rp = root_port_number(dev);
 232
 233                 if (!is_rp_enabled(rp)) {
 234
 235                         /* Configure shared resource clock gating. */
 236                         if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
 237                                 pci_or_config8(dev, 0xe1, 0x3c);
 238
 239                         if (!is_lp) {
 240                                 if (rp == 1 && !is_rp_enabled(2) &&
 241                                     !is_rp_enabled(3) && !is_rp_enabled(4)) {
 242                                         pci_or_config8(dev, 0xe2, 1);
 243                                         pci_or_config8(dev, 0xe1, 1 << 7);
 244                                 }
 245                                 if (rp == 5 && !is_rp_enabled(6) &&
 246                                     !is_rp_enabled(7) && !is_rp_enabled(8)) {
 247                                         pci_or_config8(dev, 0xe2, 1);
 248                                         pci_or_config8(dev, 0xe1, 1 << 7);
 249                                 }
 250                                 continue;
 251                         }
 252
 253                         pci_or_config8(dev, 0xe2, 3 << 4);
 254                         pci_or_config32(dev, 0x420, 1 << 31);
 255
 256                         /* Per-Port CLKREQ# handling. */
 257                         if (is_lp && gpio_is_native(18 + rp - 1))
 258                                 pci_or_config32(dev, 0x420, 3 << 29);
 259
 260                         /* Enable static clock gating. */
 261                         if (rp == 1 && !is_rp_enabled(2) &&
 262                             !is_rp_enabled(3) && !is_rp_enabled(4)) {
 263                                 pci_or_config8(dev, 0xe2, 1);
 264                                 pci_or_config8(dev, 0xe1, 1 << 7);
 265                         } else if (rp == 5 || rp == 6) {
 266                                 pci_or_config8(dev, 0xe2, 1);
 267                                 pci_or_config8(dev, 0xe1, 1 << 7);
 268                         }
 269                         continue;
 270                 }
 271
 272                 enabled_ports++;
 273
 274                 /* Enable dynamic clock gating. */
 275                 pci_or_config8(dev, 0xe1, 0x03);
 276
 277                 if (is_lp) {
 278                         pci_or_config8(dev, 0xe2, 1 << 6);
 279                         pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2));
 280                 }
 281
 282                 /* Update PECR1 register. */
 283                 pci_or_config8(dev, 0xe8, 1);
 284
 285                 pci_or_config8(dev, 0x324, 1 << 5);
 286
 287                 /* Per-Port CLKREQ# handling. */
 288                 if (is_lp && gpio_is_native(18 + rp - 1))
 289                         pci_or_config32(dev, 0x420, 3 << 29);
 290
 291                 /* Configure shared resource clock gating. */
 292                 if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
 293                         pci_or_config8(dev, 0xe1, 0x3c);
 294         }
 295
 296         if (!enabled_ports && is_lp && rpc.ports[0])
 297                 pci_or_config8(rpc.ports[0], 0xe1, 1 << 6);
 298 }
 299
 300 static void root_port_commit_config(void)
 301 {
 302         int i;
 303
 304         /* If the first root port is disabled the coalesce ports. */
 305         if (!is_rp_enabled(1))
 306                 rpc.coalesce = true;
 307
 308         /* Perform clock gating configuration. */
 309         pcie_enable_clock_gating();
 310
 311         for (i = 0; i < rpc.num_ports; i++) {
 312                 struct device *dev;
 313
 314                 dev = rpc.ports[i];
 315
 316                 if (dev == NULL) {
 317                         printk(BIOS_ERR, "Root Port %d device is NULL?\n", i+1);
 318                         continue;
 319                 }
 320
 321                 if (dev->enabled)
 322                         continue;
 323
 324                 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
 325
 326                 /* Ensure memory, io, and bus master are all disabled */
 327                 pci_and_config16(dev, PCI_COMMAND,
 328                                 ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 329
 330                 /* Disable this device if possible */
 331                 pch_disable_devfn(dev);
 332         }
 333
 334         if (rpc.coalesce) {
 335                 int current_func;
 336
 337                 /* For all Root Ports N enabled ports get assigned the lower
 338                  * PCI function number. The disabled ones get upper PCI
 339                  * function numbers. */
 340                 current_func = 0;
 341                 for (i = 0; i < rpc.num_ports; i++) {
 342                         if (!is_rp_enabled(i + 1))
 343                                 continue;
 344                         pch_pcie_device_set_func(i, current_func);
 345                         current_func++;
 346                 }
 347
 348                 /* Allocate the disabled devices' PCI function number. */
 349                 for (i = 0; i < rpc.num_ports; i++) {
 350                         if (is_rp_enabled(i + 1))
 351                                 continue;
 352                         pch_pcie_device_set_func(i, current_func);
 353                         current_func++;
 354                 }
 355         }
 356
 357         printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
 358                rpc.orig_rpfn, rpc.new_rpfn);
 359         RCBA32(RPFN) = rpc.new_rpfn;
 360 }
 361
 362 static void root_port_mark_disable(struct device *dev)
 363 {
 364         /* Mark device as disabled. */
 365         dev->enabled = 0;
 366         /* Mark device to be hidden. */
 367         rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
 368 }
 369
 370 static void root_port_check_disable(struct device *dev)
 371 {
 372         int rp;
 373         int is_lp;
 374
 375         /* Device already disabled. */
 376         if (!dev->enabled) {
 377                 root_port_mark_disable(dev);
 378                 return;
 379         }
 380
 381         rp = root_port_number(dev);
 382
 383         /* Is the GbE port mapped to this Root Port? */
 384         if (rp == rpc.gbe_port) {
 385                 root_port_mark_disable(dev);
 386                 return;
 387         }
 388
 389         is_lp = pch_is_lp();
 390
 391         /* Check Root Port Configuration. */
 392         switch (rp) {
 393                 case 2:
 394                         /* Root Port 2 is disabled for all lane configurations
 395                          * but config 00b (4x1 links). */
 396                         if ((rpc.strpfusecfg1 >> 14) & 0x3) {
 397                                 root_port_mark_disable(dev);
 398                                 return;
 399                         }
 400                         break;
 401                 case 3:
 402                         /* Root Port 3 is disabled in config 11b (1x4 links). */
 403                         if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
 404                                 root_port_mark_disable(dev);
 405                                 return;
 406                         }
 407                         break;
 408                 case 4:
 409                         /* Root Port 4 is disabled in configs 11b (1x4 links)
 410                          * and 10b (2x2 links). */
 411                         if ((rpc.strpfusecfg1 >> 14) & 0x2) {
 412                                 root_port_mark_disable(dev);
 413                                 return;
 414                         }
 415                         break;
 416                 case 6:
 417                         if (is_lp)
 418                                 break;
 419                         /* Root Port 6 is disabled for all lane configurations
 420                          * but config 00b (4x1 links). */
 421                         if ((rpc.strpfusecfg2 >> 14) & 0x3) {
 422                                 root_port_mark_disable(dev);
 423                                 return;
 424                         }
 425                         break;
 426                 case 7:
 427                         if (is_lp)
 428                                 break;
 429                         /* Root Port 7 is disabled in config 11b (1x4 links). */
 430                         if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) {
 431                                 root_port_mark_disable(dev);
 432                                 return;
 433                         }
 434                         break;
 435                 case 8:
 436                         if (is_lp)
 437                                 break;
 438                         /* Root Port 8 is disabled in configs 11b (1x4 links)
 439                          * and 10b (2x2 links). */
 440                         if ((rpc.strpfusecfg2 >> 14) & 0x2) {
 441                                 root_port_mark_disable(dev);
 442                                 return;
 443                         }
 444                         break;
 445         }
 446
 447         /* Check Pin Ownership. */
 448         if (is_lp) {
 449                 switch (rp) {
 450                 case 1:
 451                         /* Bit 0 is Root Port 1 ownership. */
 452                         if ((rpc.pin_ownership & 0x1) == 0) {
 453                                 root_port_mark_disable(dev);
 454                                 return;
 455                         }
 456                         break;
 457                 case 2:
 458                         /* Bit 2 is Root Port 2 ownership. */
 459                         if ((rpc.pin_ownership & 0x4) == 0) {
 460                                 root_port_mark_disable(dev);
 461                                 return;
 462                         }
 463                         break;
 464                 case 6:
 465                         /* Bits 7:4 are Root Port 6 pin-lane ownership. */
 466                         if ((rpc.pin_ownership & 0xf0) == 0) {
 467                                 root_port_mark_disable(dev);
 468                                 return;
 469                         }
 470                         break;
 471                 }
 472         } else {
 473                 switch (rp) {
 474                 case 1:
 475                         /* Bits 4 and 0 are Root Port 1 ownership. */
 476                         if ((rpc.pin_ownership & 0x11) == 0) {
 477                                 root_port_mark_disable(dev);
 478                                 return;
 479                         }
 480                         break;
 481                 case 2:
 482                         /* Bits 5 and 2 are Root Port 2 ownership. */
 483                         if ((rpc.pin_ownership & 0x24) == 0) {
 484                                 root_port_mark_disable(dev);
 485                                 return;
 486                         }
 487                         break;
 488                 }
 489         }
 490 }
 491
 492 static void pcie_add_0x0202000_iobp(u32 reg)
 493 {
 494         u32 reg32;
 495
 496         reg32 = pch_iobp_read(reg);
 497         reg32 += (0x2 << 16) | (0x2 << 8);
 498         pch_iobp_write(reg, reg32);
 499 }
 500
 501 static void pch_pcie_early(struct device *dev)
 502 {
 503         struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 504         int do_aspm = 0;
 505         int rp = root_port_number(dev);
 506         int is_lp = pch_is_lp();
 507
 508         if (is_lp) {
 509                 switch (rp) {
 510                 case 1:
 511                 case 2:
 512                 case 3:
 513                 case 4:
 514                         /*
 515                          * Bits 31:28 of b0d28f0 0x32c register correspond to
 516                          * Root Ports 4:1.
 517                          */
 518                         do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
 519                         break;
 520                 case 5:
 521                         /*
 522                          * Bit 28 of b0d28f4 0x32c register correspond to
 523                          * Root Ports 4:1.
 524                          */
 525                         do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
 526                         break;
 527                 case 6:
 528                         /*
 529                          * Bit 28 of b0d28f5 0x32c register correspond to
 530                          * Root Ports 4:1.
 531                          */
 532                         do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
 533                         break;
 534                 }
 535         } else {
 536                 switch (rp) {
 537                 case 1:
 538                 case 2:
 539                 case 3:
 540                 case 4:
 541                         /*
 542                          * Bits 31:28 of b0d28f0 0x32c register correspond to
 543                          * Root Ports 4:1.
 544                          */
 545                         do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
 546                         break;
 547                 case 5:
 548                 case 6:
 549                 case 7:
 550                 case 8:
 551                         /*
 552                          * Bits 31:28 of b0d28f4 0x32c register correspond to
 553                          * Root Ports 8:5.
 554                          */
 555                         do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5)));
 556                         break;
 557                 }
 558         }
 559
 560         /* Allow ASPM to be forced on in devicetree */
 561         if (config && (config->pcie_port_force_aspm & (1 << (rp - 1))))
 562                 do_aspm = 1;
 563
 564         printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",
 565                rp, do_aspm ? "en" : "dis");
 566
 567         if (do_aspm) {
 568                 /* Set ASPM bits in MPC2 register. */
 569                 pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
 570
 571                 /* Set unique clock exit latency in MPC register. */
 572                 pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
 573
 574                 /* Set L1 exit latency in LCAP register. */
 575                 pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
 576
 577                 if (is_lp) {
 578                         switch (rp) {
 579                         case 1:
 580                                 pcie_add_0x0202000_iobp(0xe9002440);
 581                                 break;
 582                         case 2:
 583                                 pcie_add_0x0202000_iobp(0xe9002640);
 584                                 break;
 585                         case 3:
 586                                 pcie_add_0x0202000_iobp(0xe9000840);
 587                                 break;
 588                         case 4:
 589                                 pcie_add_0x0202000_iobp(0xe9000a40);
 590                                 break;
 591                         case 5:
 592                                 pcie_add_0x0202000_iobp(0xe9000c40);
 593                                 pcie_add_0x0202000_iobp(0xe9000e40);
 594                                 pcie_add_0x0202000_iobp(0xe9001040);
 595                                 pcie_add_0x0202000_iobp(0xe9001240);
 596                                 break;
 597                         case 6:
 598                                 /* Update IOBP based on lane ownership. */
 599                                 if (rpc.pin_ownership & (1 << 4))
 600                                         pcie_add_0x0202000_iobp(0xea002040);
 601                                 if (rpc.pin_ownership & (1 << 5))
 602                                         pcie_add_0x0202000_iobp(0xea002240);
 603                                 if (rpc.pin_ownership & (1 << 6))
 604                                         pcie_add_0x0202000_iobp(0xea002440);
 605                                 if (rpc.pin_ownership & (1 << 7))
 606                                         pcie_add_0x0202000_iobp(0xea002640);
 607                                 break;
 608                         }
 609                 } else {
 610                         switch (rp) {
 611                         case 1:
 612                                 if ((rpc.pin_ownership & 0x3) == 1)
 613                                         pcie_add_0x0202000_iobp(0xe9002e40);
 614                                 else
 615                                         pcie_add_0x0202000_iobp(0xea002040);
 616                                 break;
 617                         case 2:
 618                                 if ((rpc.pin_ownership & 0xc) == 0x4)
 619                                         pcie_add_0x0202000_iobp(0xe9002c40);
 620                                 else
 621                                         pcie_add_0x0202000_iobp(0xea002240);
 622                                 break;
 623                         case 3:
 624                                 pcie_add_0x0202000_iobp(0xe9002a40);
 625                                 break;
 626                         case 4:
 627                                 pcie_add_0x0202000_iobp(0xe9002840);
 628                                 break;
 629                         case 5:
 630                                 pcie_add_0x0202000_iobp(0xe9002640);
 631                                 break;
 632                         case 6:
 633                                 pcie_add_0x0202000_iobp(0xe9002440);
 634                                 break;
 635                         case 7:
 636                                 pcie_add_0x0202000_iobp(0xe9002240);
 637                                 break;
 638                         case 8:
 639                                 pcie_add_0x0202000_iobp(0xe9002040);
 640                                 break;
 641                         }
 642                 }
 643
 644                 pci_and_config32(dev, 0x338, ~(1 << 26));
 645         }
 646
 647         /* Enable LTR in Root Port. Disable OBFF. */
 648         pci_update_config32(dev, 0x64, ~(3 << 18), 1 << 11);
 649         pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10);
 650
 651         pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
 652
 653         /* Set L1 exit latency in LCAP register. */
 654         if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
 655                 pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
 656         else
 657                 pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
 658
 659         pci_update_config32(dev, 0x314, 0, 0x743a361b);
 660
 661         /* Set Common Clock Exit Latency in MPC register. */
 662         pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
 663
 664         pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74);
 665
 666         /* Set Invalid Receive Range Check Enable in MPC register. */
 667         pci_or_config32(dev, 0xd8, 1 << 25);
 668
 669         pci_and_config8(dev, 0xf5, 0x3f);
 670
 671         if (rp == 1 || rp == 5 || (is_lp && rp == 6))
 672                 pci_and_config8(dev, 0xf7, ~0x0c);
 673
 674         /* Set EOI forwarding disable. */
 675         pci_or_config32(dev, 0xd4, 1 << 1);
 676
 677         /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
 678         if (CONFIG(PCIEXP_AER))
 679                 pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001);
 680         else
 681                 pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29));
 682
 683         /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
 684         if (CONFIG(PCIEXP_L1_SUB_STATE))
 685                 pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
 686         else
 687                 pci_update_config32(dev, 0x200, ~0xfffff, 0);
 688
 689         if (is_lp)
 690                 pci_or_config32(dev, 0x100, 1 << 29);
 691
 692         /* Read and write back write-once capability registers. */
 693         pci_update_config32(dev, 0x34, ~0, 0);
 694         pci_update_config32(dev, 0x40, ~0, 0);
 695         pci_update_config32(dev, 0x80, ~0, 0);
 696         pci_update_config32(dev, 0x90, ~0, 0);
 697 }
 698
 699 static void pch_pcie_init(struct device *dev)
 700 {
 701         printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
 702
 703         /* Enable SERR */
 704         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 705
 706         /* Enable Bus Master */
 707         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 708
 709         /* Set Cache Line Size to 0x10 */
 710         // This has no effect but the OS might expect it
 711         pci_write_config8(dev, 0x0c, 0x10);
 712
 713         pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
 714
 715         /* Clear errors in status registers */
 716         pci_update_config16(dev, 0x06, ~0, 0);
 717         pci_update_config16(dev, 0x1e, ~0, 0);
 718 }
 719
 720 static void pch_pcie_enable(struct device *dev)
 721 {
 722         /* Add this device to the root port config structure. */
 723         root_port_init_config(dev);
 724
 725         /* Check to see if this Root Port should be disabled. */
 726         root_port_check_disable(dev);
 727
 728         /* Power Management init before enumeration */
 729         if (dev->enabled)
 730                 pch_pcie_early(dev);
 731
 732         /*
 733          * When processing the last PCIe root port we can now
 734          * update the Root Port Function Number and Hide register.
 735          */
 736         if (root_port_is_last(dev))
 737                 root_port_commit_config();
 738 }
 739
 740 static struct device_operations device_ops = {
 741         .read_resources         = pci_bus_read_resources,
 742         .set_resources          = pci_dev_set_resources,
 743         .enable_resources       = pci_bus_enable_resources,
 744         .init                   = pch_pcie_init,
 745         .enable                 = pch_pcie_enable,
 746         .scan_bus               = pciexp_scan_bridge,
 747         .ops_pci                = &pci_dev_ops_pci,
 748 };
 749
 750 static const unsigned short pci_device_ids[] = {
 751         PCI_DID_INTEL_LPT_H_PCIE_RP1,
 752         PCI_DID_INTEL_LPT_H_PCIE_RP2,
 753         PCI_DID_INTEL_LPT_H_PCIE_RP3,
 754         PCI_DID_INTEL_LPT_H_PCIE_RP4,
 755         PCI_DID_INTEL_LPT_H_PCIE_RP5,
 756         PCI_DID_INTEL_LPT_H_PCIE_RP6,
 757         PCI_DID_INTEL_LPT_H_PCIE_RP7,
 758         PCI_DID_INTEL_LPT_H_PCIE_RP8,
 759         PCI_DID_INTEL_LPT_LP_PCIE_RP1,
 760         PCI_DID_INTEL_LPT_LP_PCIE_RP2,
 761         PCI_DID_INTEL_LPT_LP_PCIE_RP3,
 762         PCI_DID_INTEL_LPT_LP_PCIE_RP4,
 763         PCI_DID_INTEL_LPT_LP_PCIE_RP5,
 764         PCI_DID_INTEL_LPT_LP_PCIE_RP6,
 765         0
 766 };
 767
 768 static const struct pci_driver pch_pcie __pci_driver = {
 769         .ops     = &device_ops,
 770         .vendor  = PCI_VID_INTEL,
 771         .devices = pci_device_ids,
 772 };