src/southbridge/intel/lynxpoint/serialio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <acpi/acpi_gnvs.h>
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <soc/nvs.h>
  11 #include <types.h>
  12 #include "chip.h"
  13 #include "iobp.h"
  14 #include "pch.h"
  15
  16 /* Enable clock in PCI mode */
  17 static void serialio_enable_clock(struct resource *bar0)
  18 {
  19         u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
  20         reg32 |= SIO_REG_PPR_CLOCK_EN;
  21         write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
  22 }
  23
  24 static bool serialio_uart_is_debug(struct device *dev)
  25 {
  26         if (CONFIG(SERIALIO_UART_CONSOLE)) {
  27                 switch (dev->path.pci.devfn) {
  28                 case PCH_DEVFN_UART0:
  29                         return CONFIG_UART_FOR_CONSOLE == 0;
  30                 case PCH_DEVFN_UART1:
  31                         return CONFIG_UART_FOR_CONSOLE == 1;
  32                 }
  33         }
  34         return 0;
  35 }
  36
  37 /* Put Serial IO D21:F0-F6 device into desired mode. */
  38 static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode)
  39 {
  40         u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT;
  41
  42         /* Snoop select 1. */
  43         portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1);
  44
  45         /* Set interrupt pin. */
  46         portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin);
  47
  48         if (acpi_mode) {
  49                 /* Enable ACPI interrupt mode. */
  50                 portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN;
  51
  52                 /* Disable PCI config space. */
  53                 portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS;
  54         }
  55
  56         pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl);
  57 }
  58
  59 /* Put Serial IO D23:F0 device into desired mode. */
  60 static void serialio_d23_mode(int acpi_mode)
  61 {
  62         u32 portctrl = 0;
  63
  64         /* Snoop select 1. */
  65         pch_iobp_update(SIO_IOBP_PORTCTRL1, 0,
  66                         SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1));
  67
  68         if (acpi_mode) {
  69                 /* Enable ACPI interrupt mode. */
  70                 portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN;
  71
  72                 /* Disable PCI config space. */
  73                 portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS;
  74         }
  75
  76         pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl);
  77 }
  78
  79 /* Enable LTR Auto Mode for D21:F1-F6. */
  80 static void serialio_d21_ltr(struct resource *bar0)
  81 {
  82         u32 reg;
  83
  84         /* 1. Program BAR0 + 808h[2] = 0b */
  85         reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
  86         reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
  87         write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
  88
  89         /* 2. Program BAR0 + 804h[1:0] = 00b */
  90         reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
  91         reg &= ~SIO_REG_PPR_RST_ASSERT;
  92         write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
  93
  94         /* 3. Program BAR0 + 804h[1:0] = 11b */
  95         reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
  96         reg |= SIO_REG_PPR_RST_ASSERT;
  97         write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
  98
  99         /* 4. Program BAR0 + 814h[31:0] = 00000000h */
 100         write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
 101 }
 102
 103 /* Enable LTR Auto Mode for D23:F0. */
 104 static void serialio_d23_ltr(struct resource *bar0)
 105 {
 106         u32 reg;
 107
 108         /* Program BAR0 + 1008h[2] = 1b */
 109         reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
 110         reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
 111         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
 112
 113         /* Program BAR0 + 1010h = 0x00000000 */
 114         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
 115
 116         /* Program BAR0 + 3Ch[30] = 1b */
 117         reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
 118         reg |= SIO_REG_SDIO_PPR_CMD12_B30;
 119         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
 120 }
 121
 122 /* Select I2C voltage of 1.8V or 3.3V. */
 123 static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
 124 {
 125         u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
 126         reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
 127         reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
 128         write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
 129 }
 130
 131 /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
 132 static void serialio_init_once(int acpi_mode)
 133 {
 134         if (acpi_mode) {
 135                 /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */
 136                 RCBA32_OR(ACPIIRQEN, (1 << 13) | (1 << 7) | (1 << 6) | (1 << 5));
 137         }
 138
 139         /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */
 140         pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f);
 141
 142         /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
 143         pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
 144 }
 145
 146 static void update_bars(int sio_index, u32 bar0, u32 bar1)
 147 {
 148         /* Find ACPI NVS to update BARs */
 149         struct global_nvs *gnvs = acpi_get_gnvs();
 150         if (!gnvs)
 151                 return;
 152
 153         gnvs->s0b[sio_index] = bar0;
 154         gnvs->s1b[sio_index] = bar1;
 155 }
 156
 157 static void serialio_init(struct device *dev)
 158 {
 159         struct southbridge_intel_lynxpoint_config *config = config_of(dev);
 160         struct resource *bar0, *bar1;
 161         int sio_index = -1;
 162
 163         printk(BIOS_DEBUG, "Initializing Serial IO device\n");
 164
 165         /* Ensure memory and bus master are enabled */
 166         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 167
 168         /* Find BAR0 and BAR1 */
 169         bar0 = probe_resource(dev, PCI_BASE_ADDRESS_0);
 170         if (!bar0)
 171                 return;
 172         bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1);
 173         if (!bar1)
 174                 return;
 175
 176         if (!config->sio_acpi_mode)
 177                 serialio_enable_clock(bar0);
 178
 179         switch (dev->path.pci.devfn) {
 180         case PCH_DEVFN_SDMA: /* SDMA */
 181                 sio_index = SIO_ID_SDMA;
 182                 serialio_init_once(config->sio_acpi_mode);
 183                 serialio_d21_mode(sio_index, SIO_PIN_INTB,
 184                                   config->sio_acpi_mode);
 185                 break;
 186         case PCH_DEVFN_I2C0: /* I2C0 */
 187                 sio_index = SIO_ID_I2C0;
 188                 serialio_d21_ltr(bar0);
 189                 serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
 190                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 191                                   config->sio_acpi_mode);
 192                 break;
 193         case PCH_DEVFN_I2C1: /* I2C1 */
 194                 sio_index = SIO_ID_I2C1;
 195                 serialio_d21_ltr(bar0);
 196                 serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
 197                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 198                                   config->sio_acpi_mode);
 199                 break;
 200         case PCH_DEVFN_SPI0: /* SPI0 */
 201                 sio_index = SIO_ID_SPI0;
 202                 serialio_d21_ltr(bar0);
 203                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 204                                   config->sio_acpi_mode);
 205                 break;
 206         case PCH_DEVFN_SPI1: /* SPI1 */
 207                 sio_index = SIO_ID_SPI1;
 208                 serialio_d21_ltr(bar0);
 209                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 210                                   config->sio_acpi_mode);
 211                 break;
 212         case PCH_DEVFN_UART0: /* UART0 */
 213                 sio_index = SIO_ID_UART0;
 214                 if (!serialio_uart_is_debug(dev))
 215                         serialio_d21_ltr(bar0);
 216                 serialio_d21_mode(sio_index, SIO_PIN_INTD,
 217                                   config->sio_acpi_mode);
 218                 break;
 219         case PCH_DEVFN_UART1: /* UART1 */
 220                 sio_index = SIO_ID_UART1;
 221                 if (!serialio_uart_is_debug(dev))
 222                         serialio_d21_ltr(bar0);
 223                 serialio_d21_mode(sio_index, SIO_PIN_INTD,
 224                                   config->sio_acpi_mode);
 225                 break;
 226         case PCH_DEVFN_SDIO: /* SDIO */
 227                 sio_index = SIO_ID_SDIO;
 228                 serialio_d23_ltr(bar0);
 229                 serialio_d23_mode(config->sio_acpi_mode);
 230                 break;
 231         default:
 232                 return;
 233         }
 234
 235         /* Save BAR0 and BAR1 to ACPI NVS */
 236         if (config->sio_acpi_mode)
 237                 update_bars(sio_index, (u32)bar0->base, (u32)bar1->base);
 238 }
 239
 240 static void serialio_read_resources(struct device *dev)
 241 {
 242         pci_dev_read_resources(dev);
 243
 244         /* Set the configured UART base address for the debug port */
 245         if (CONFIG(SERIALIO_UART_CONSOLE) && serialio_uart_is_debug(dev)) {
 246                 struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 247                 res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
 248                 res->size = 0x1000;
 249                 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 250         }
 251 }
 252
 253 static struct device_operations device_ops = {
 254         .read_resources         = serialio_read_resources,
 255         .set_resources          = pci_dev_set_resources,
 256         .enable_resources       = pci_dev_enable_resources,
 257         .init                   = serialio_init,
 258         .ops_pci                = &pci_dev_ops_pci,
 259 };
 260
 261 static const unsigned short pci_device_ids[] = {
 262         PCI_DID_INTEL_LPT_LP_SDMA,
 263         PCI_DID_INTEL_LPT_LP_I2C0,
 264         PCI_DID_INTEL_LPT_LP_I2C1,
 265         PCI_DID_INTEL_LPT_LP_GSPI0,
 266         PCI_DID_INTEL_LPT_LP_GSPI1,
 267         PCI_DID_INTEL_LPT_LP_UART0,
 268         PCI_DID_INTEL_LPT_LP_UART1,
 269         PCI_DID_INTEL_LPT_LP_SD,
 270         0
 271 };
 272
 273 static const struct pci_driver pch_pcie __pci_driver = {
 274         .ops     = &device_ops,
 275         .vendor  = PCI_VID_INTEL,
 276         .devices = pci_device_ids,
 277 };