src/southbridge/intel/lynxpoint/usb_ehci.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <delay.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pci_ids.h>
   8 #include <device/pci_ehci.h>
   9 #include <device/mmio.h>
  10 #include <device/pci_ops.h>
  11 #include "iobp.h"
  12 #include "pch.h"
  13
  14 #ifdef __SIMPLE_DEVICE__
  15
  16 void usb_ehci_disable(pci_devfn_t dev)
  17 {
  18         /* Set 0xDC[0]=1 */
  19         pci_or_config32(dev, 0xdc, (1 << 0));
  20
  21         /* Set D3Hot state and disable PME */
  22         pci_update_config16(dev, EHCI_PWR_CTL_STS, ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK),
  23                             PWR_CTL_SET_D3);
  24
  25         /* Clear memory and bus master */
  26         pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
  27
  28         pci_and_config16(dev, PCI_COMMAND,
  29                         ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
  30
  31         /* Disable device */
  32         switch (dev) {
  33         case PCH_EHCI1_DEV:
  34                 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
  35                 break;
  36         case PCH_EHCI2_DEV:
  37                 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
  38                 break;
  39         }
  40 }
  41
  42 /* Handler for EHCI controller on entry to S3/S4/S5 */
  43 void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
  44 {
  45         u32 reg32;
  46         u8 *bar0_base;
  47         u16 pwr_state;
  48         u16 pci_cmd;
  49
  50         /* Check if the controller is disabled or not present */
  51         bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
  52         if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff)
  53                 return;
  54         pci_cmd = pci_read_config16(dev, PCI_COMMAND);
  55
  56         switch (slp_typ) {
  57         case ACPI_S4:
  58         case ACPI_S5:
  59                 /* Check if controller is in D3 power state */
  60                 pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS);
  61                 if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
  62                         /* Put in D0 */
  63                         u32 new_state = pwr_state & ~PWR_CTL_SET_MASK;
  64                         new_state |= PWR_CTL_SET_D0;
  65                         pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state);
  66
  67                         /* Make sure memory bar is set */
  68                         pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base);
  69
  70                         /* Make sure memory space is enabled */
  71                         pci_write_config16(dev, PCI_COMMAND, pci_cmd |
  72                                    PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  73                 }
  74
  75                 /*
  76                  * If Run/Stop (bit0) is clear in USB2.0_CMD:
  77                  * - Clear Async Schedule Enable (bit5) and
  78                  * - Clear Periodic Schedule Enable (bit4) and
  79                  * - Set Run/Stop (bit0)
  80                  */
  81                 reg32 = read32(bar0_base + EHCI_USB_CMD);
  82                 if (reg32 & EHCI_USB_CMD_RUN) {
  83                         reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE);
  84                         reg32 |= EHCI_USB_CMD_RUN;
  85                         write32(bar0_base + EHCI_USB_CMD, reg32);
  86                 }
  87
  88                 /* Check for Port Enabled in PORTSC(0) (RMH) */
  89                 reg32 = read32(bar0_base + EHCI_PORTSC(0));
  90                 if (reg32 & EHCI_PORTSC_ENABLED) {
  91                         /* Set suspend bit in PORTSC if not already set */
  92                         if (!(reg32 & EHCI_PORTSC_SUSPEND)) {
  93                                 reg32 |= EHCI_PORTSC_SUSPEND;
  94                                 write32(bar0_base + EHCI_PORTSC(0), reg32);
  95                         }
  96
  97                         /* Delay 25ms !! */
  98                         udelay(25 * 1000);
  99
 100                         /* Clear Run/Stop bit */
 101                         reg32 = read32(bar0_base + EHCI_USB_CMD);
 102                         reg32 &= EHCI_USB_CMD_RUN;
 103                         write32(bar0_base + EHCI_USB_CMD, reg32);
 104                 }
 105
 106                 /* Restore state to D3 if that is what it was at the start */
 107                 if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
 108                         /* Restore pci command reg */
 109                         pci_write_config16(dev, PCI_COMMAND, pci_cmd);
 110
 111                         /* Enable D3 */
 112                         pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state);
 113                 }
 114         }
 115 }
 116
 117 #else /* !__SIMPLE_DEVICE__ */
 118
 119 static void usb_ehci_clock_gating(struct device *dev)
 120 {
 121         /* IOBP 0xE5004001[7:6] = 11b */
 122         pch_iobp_update(0xe5004001, ~0, (1 << 7) | (1 << 6));
 123
 124         /* Dx:F0:DCh[5,2,1] = 111b
 125          * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */
 126         pci_or_config32(dev, 0xdc, (1 << 5) | (1 << 2) | (1 << 1));
 127
 128         /* Dx:F0:78h[1:0] = 11b */
 129         pci_or_config32(dev, 0x78, (1 << 1) | (1 << 0));
 130 }
 131
 132 static void usb_ehci_init(struct device *dev)
 133 {
 134         printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 135
 136         usb_ehci_clock_gating(dev);
 137
 138         /* Disable Wake on Disconnect in RMH */
 139         RCBA32_OR(0x35b0, 0x00000022);
 140
 141         printk(BIOS_DEBUG, "done.\n");
 142 }
 143
 144 static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
 145                                    unsigned int device)
 146 {
 147         u8 access_cntl;
 148
 149         access_cntl = pci_read_config8(dev, 0x80);
 150
 151         /* Enable writes to protected registers. */
 152         pci_write_config8(dev, 0x80, access_cntl | 1);
 153
 154         pci_dev_set_subsystem(dev, vendor, device);
 155
 156         /* Restore protection. */
 157         pci_write_config8(dev, 0x80, access_cntl);
 158 }
 159
 160 static struct pci_operations lops_pci = {
 161         .set_subsystem  = &usb_ehci_set_subsystem,
 162 };
 163
 164 static struct device_operations usb_ehci_ops = {
 165         .read_resources         = pci_ehci_read_resources,
 166         .set_resources          = pci_dev_set_resources,
 167         .enable_resources       = pci_dev_enable_resources,
 168         .init                   = usb_ehci_init,
 169         .ops_pci                = &lops_pci,
 170 };
 171
 172 static const unsigned short pci_device_ids[] = {
 173         PCI_DID_INTEL_LPT_LP_EHCI,
 174         PCI_DID_INTEL_LPT_H_EHCI_1,
 175         PCI_DID_INTEL_LPT_H_EHCI_2,
 176         PCI_DID_INTEL_LPT_H_EHCI_1_9,
 177         PCI_DID_INTEL_LPT_H_EHCI_2_9,
 178         0
 179 };
 180
 181 static const struct pci_driver pch_usb_ehci __pci_driver = {
 182         .ops     = &usb_ehci_ops,
 183         .vendor  = PCI_VID_INTEL,
 184         .devices = pci_device_ids,
 185 };
 186
 187 #endif /* !__SIMPLE_DEVICE__ */