src/cpu/intel/microcode/microcode.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Microcode update for Intel PIII and later CPUs */
   4
   5 #include <cbfs.h>
   6 #include <console/console.h>
   7 #include <cpu/cpu.h>
   8 #include <cpu/intel/microcode.h>
   9 #include <cpu/x86/msr.h>
  10 #include <smp/spinlock.h>
  11 #include <types.h>
  12
  13 DECLARE_SPIN_LOCK(microcode_lock)
  14
  15 struct microcode {
  16         u32 hdrver;     /* Header Version */
  17         u32 rev;        /* Update Revision */
  18         u32 date;       /* Date */
  19         u32 sig;        /* Processor Signature */
  20
  21         u32 cksum;      /* Checksum */
  22         u32 ldrver;     /* Loader Revision */
  23         u32 pf;         /* Processor Flags */
  24
  25         u32 data_size;  /* Data Size */
  26         u32 total_size; /* Total Size */
  27
  28         u32 reserved[3];
  29 };
  30
  31 struct ext_sig_table {
  32         u32 ext_sig_cnt;
  33         u32 ext_tbl_chksm;
  34         u32 res[3];
  35 };
  36
  37 struct ext_sig_entry {
  38         u32 sig;
  39         u32 pf;
  40         u32 chksm;
  41 };
  42
  43 static inline u32 read_microcode_rev(void)
  44 {
  45         /* Some Intel CPUs can be very finicky about the
  46          * CPUID sequence used.  So this is implemented in
  47          * assembly so that it works reliably.
  48          */
  49         msr_t msr;
  50         asm volatile (
  51                 "xorl %%eax, %%eax\n\t"
  52                 "xorl %%edx, %%edx\n\t"
  53                 "movl $0x8b, %%ecx\n\t"
  54                 "wrmsr\n\t"
  55                 "movl $0x01, %%eax\n\t"
  56                 "cpuid\n\t"
  57                 "movl $0x08b, %%ecx\n\t"
  58                 "rdmsr\n\t"
  59                 : /* outputs */
  60                 "=a" (msr.lo), "=d" (msr.hi)
  61                 : /* inputs */
  62                 : /* trashed */
  63                  "ebx", "ecx"
  64         );
  65         return msr.hi;
  66 }
  67
  68 #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
  69
  70 static int load_microcode(const struct microcode *ucode_patch)
  71 {
  72         u32 current_rev;
  73         msr_t msr;
  74
  75         msr.lo = (unsigned long)ucode_patch + sizeof(struct microcode);
  76         msr.hi = 0;
  77         wrmsr(IA32_BIOS_UPDT_TRIG, msr);
  78
  79         current_rev = read_microcode_rev();
  80         if (current_rev == ucode_patch->rev) {
  81                 printk(BIOS_INFO, "microcode: updated to revision "
  82                     "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
  83                     ucode_patch->date & 0xffff, (ucode_patch->date >> 24) & 0xff,
  84                     (ucode_patch->date >> 16) & 0xff);
  85                 return 0;
  86         }
  87
  88         return -1;
  89 }
  90
  91 void intel_microcode_load_unlocked(const void *microcode_patch)
  92 {
  93         u32 current_rev;
  94         const struct microcode *m = microcode_patch;
  95
  96         if (!m) {
  97                 printk(BIOS_WARNING, "microcode: failed because no ucode was found\n");
  98                 return;
  99         }
 100
 101         current_rev = read_microcode_rev();
 102
 103         /* No use loading the same revision. */
 104         if (current_rev == m->rev) {
 105                 printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n");
 106                 return;
 107         }
 108
 109 #if ENV_RAMSTAGE
 110         /*SoC specific check to update microcode*/
 111         if (soc_skip_ucode_update(current_rev, m->rev)) {
 112                 printk(BIOS_DEBUG, "Skip microcode update\n");
 113                 return;
 114         }
 115 #endif
 116
 117         printk(BIOS_INFO, "microcode: load microcode patch\n");
 118         if (load_microcode(m) < 0)
 119                 printk(BIOS_ERR, "microcode: Update failed\n");
 120 }
 121
 122 uint32_t get_current_microcode_rev(void)
 123 {
 124         return read_microcode_rev();
 125 }
 126
 127 uint32_t get_microcode_rev(const void *microcode)
 128 {
 129         return ((struct microcode *)microcode)->rev;
 130 }
 131
 132 uint32_t get_microcode_size(const void *microcode)
 133 {
 134         return ((struct microcode *)microcode)->total_size;
 135 }
 136
 137 uint32_t get_microcode_checksum(const void *microcode)
 138 {
 139         return ((struct microcode *)microcode)->cksum;
 140 }
 141
 142
 143 static struct ext_sig_table *ucode_get_ext_sig_table(const struct microcode *ucode)
 144 {
 145         struct ext_sig_table *ext_tbl;
 146         /* header + ucode data blob size */
 147         u32 size = ucode->data_size + sizeof(struct microcode);
 148
 149         ssize_t ext_tbl_len = ucode->total_size - size;
 150
 151         if (ext_tbl_len < (ssize_t)sizeof(struct ext_sig_table))
 152                 return NULL;
 153
 154         ext_tbl = (struct ext_sig_table *)((uintptr_t)ucode + size);
 155
 156         if (ext_tbl_len < (sizeof(struct ext_sig_table) +
 157                                 ext_tbl->ext_sig_cnt * sizeof(struct ext_sig_entry)))
 158                 return NULL;
 159
 160         return ext_tbl;
 161 }
 162
 163 static const void *find_cbfs_microcode(void)
 164 {
 165         const struct microcode *ucode_updates;
 166         struct ext_sig_table *ext_tbl;
 167         size_t microcode_len;
 168         u32 eax;
 169         u32 pf, rev, sig, update_size;
 170         msr_t msr;
 171         struct cpuinfo_x86 c;
 172
 173         ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, &microcode_len);
 174         if (ucode_updates == NULL)
 175                 return NULL;
 176
 177         rev = read_microcode_rev();
 178         eax = cpuid_eax(1);
 179         get_fms(&c, eax);
 180         sig = eax;
 181
 182         pf = 0;
 183         if ((c.x86_model >= 5) || (c.x86 > 6)) {
 184                 msr = rdmsr(IA32_PLATFORM_ID);
 185                 pf = 1 << ((msr.hi >> 18) & 7);
 186         }
 187
 188         printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n",
 189                         sig, pf, rev);
 190
 191         while (microcode_len >= sizeof(*ucode_updates)) {
 192                 /* Newer microcode updates include a size field, whereas older
 193                  * containers set it at 0 and are exactly 2048 bytes long */
 194                 if (ucode_updates->total_size) {
 195                         update_size = ucode_updates->total_size;
 196                 } else {
 197                         printk(BIOS_SPEW, "Microcode size field is 0\n");
 198                         update_size = 2048;
 199                 }
 200
 201                 /* Checkpoint 1: The microcode update falls within CBFS */
 202                 if (update_size > microcode_len) {
 203                         printk(BIOS_WARNING, "Microcode header corrupted!\n");
 204                         break;
 205                 }
 206
 207                 if ((ucode_updates->sig == sig) && (ucode_updates->pf & pf))
 208                         return ucode_updates;
 209
 210
 211                 /* Check if there is extended signature table */
 212                 ext_tbl = ucode_get_ext_sig_table(ucode_updates);
 213
 214                 if (ext_tbl != NULL) {
 215                         int i;
 216                         struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
 217
 218                         for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) {
 219                                 if ((sig == entry->sig) && (pf & entry->pf)) {
 220                                         return ucode_updates;
 221                                 }
 222                         }
 223                 }
 224
 225                 ucode_updates = (void *)((char *)ucode_updates + update_size);
 226                 microcode_len -= update_size;
 227         }
 228
 229         return NULL;
 230 }
 231
 232 const void *intel_microcode_find(void)
 233 {
 234         static bool microcode_checked;
 235         static const void *ucode_update;
 236
 237         if (microcode_checked)
 238                 return ucode_update;
 239
 240         /*
 241          * Since this function caches the found microcode (NULL or a valid
 242          * microcode pointer), it is expected to be run from BSP before starting
 243          * any other APs. This sequence is not multithread safe otherwise.
 244          */
 245         ucode_update = find_cbfs_microcode();
 246         microcode_checked = true;
 247
 248         return ucode_update;
 249 }
 250
 251 void intel_update_microcode_from_cbfs(void)
 252 {
 253         const void *patch = intel_microcode_find();
 254
 255         spin_lock(&microcode_lock);
 256
 257         intel_microcode_load_unlocked(patch);
 258
 259         spin_unlock(&microcode_lock);
 260 }
 261
 262 void intel_reload_microcode(void)
 263 {
 264         if (!CONFIG(RELOAD_MICROCODE_PATCH))
 265                 return;
 266
 267         const struct microcode *m = intel_microcode_find();
 268
 269         if (!m) {
 270                 printk(BIOS_WARNING, "microcode: failed because no ucode was found\n");
 271                 return;
 272         }
 273
 274         printk(BIOS_INFO, "microcode: Re-load microcode patch\n");
 275
 276         if (load_microcode(m) < 0)
 277                 printk(BIOS_ERR, "microcode: Re-load failed\n");
 278 }
 279
 280 #if ENV_RAMSTAGE
 281 __weak int soc_skip_ucode_update(u32 current_patch_id,
 282         u32 new_patch_id)
 283 {
 284         return 0;
 285 }
 286 #endif