soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
[coreboot.git] / src / drivers / spi / atmel.c
blob2d191d9a1b57a29db9e259a0605d82d2535638bb
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <commonlib/helpers.h>
4 #include <spi_flash.h>
5 #include <spi-generic.h>
7 #include "spi_flash_internal.h"
9 /* M25Pxx-specific commands */
10 #define CMD_AT25_WREN 0x06 /* Write Enable */
11 #define CMD_AT25_WRDI 0x04 /* Write Disable */
12 #define CMD_AT25_RDSR 0x05 /* Read Status Register */
13 #define CMD_AT25_WRSR 0x01 /* Write Status Register */
14 #define CMD_AT25_READ 0x03 /* Read Data Bytes */
15 #define CMD_AT25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
16 #define CMD_AT25_PP 0x02 /* Page Program */
17 #define CMD_AT25_SE 0x20 /* Sector (4K) Erase */
18 #define CMD_AT25_BE 0xd8 /* Block (64K) Erase */
19 #define CMD_AT25_CE 0xc7 /* Chip Erase */
20 #define CMD_AT25_DP 0xb9 /* Deep Power-down */
21 #define CMD_AT25_RES 0xab /* Release from DP, and Read Signature */
23 static const struct spi_flash_part_id flash_table[] = {
25 /* AT25X16 */
26 .id[0] = 0x3015,
27 .nr_sectors_shift = 9,
30 /* AT25DF32 */
31 .id[0] = 0x47,
32 .nr_sectors_shift = 10,
35 /* AT25X64 */
36 .id[0] = 0x3017,
37 .nr_sectors_shift = 11,
40 /* AT25Q16 */
41 .id[0] = 0x4015,
42 .nr_sectors_shift = 9,
45 /* AT25Q32 */
46 .id[0] = 0x4016,
47 .nr_sectors_shift = 10,
50 /* AT25Q64 */
51 .id[0] = 0x4017,
52 .nr_sectors_shift = 11,
55 /* AT25Q128 */
56 .id[0] = 0x4018,
57 .nr_sectors_shift = 12,
61 const struct spi_flash_vendor_info spi_flash_atmel_vi = {
62 .id = VENDOR_ID_ATMEL,
63 .page_size_shift = 8,
64 .sector_size_kib_shift = 2,
65 .match_id_mask[0] = 0xffff,
66 .ids = flash_table,
67 .nr_part_ids = ARRAY_SIZE(flash_table),
68 .desc = &spi_flash_pp_0x20_sector_desc,