src/mainboard/system76/gaze15/devicetree.cb

   1 chip soc/intel/cannonlake
   2         register "common_soc_config" = "{
   3                 // Touchpad I2C bus
   4                 .i2c[0] = {
   5                         .speed = I2C_SPEED_FAST,
   6                         .rise_time_ns = 80,
   7                         .fall_time_ns = 110,
   8                 },
   9         }"
  10
  11 # CPU (soc/intel/cannonlake/cpu.c)
  12         # Power limit
  13         register "power_limits_config" = "{
  14                 .tdp_pl1_override = 45,
  15                 .tdp_pl2_override = 90,
  16         }"
  17
  18         # Enable Enhanced Intel SpeedStep
  19         register "eist_enable" = "1"
  20
  21 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  22         register "enable_c6dram" = "1"
  23
  24 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  25         # Misc
  26         register "AcousticNoiseMitigation" = "1"
  27
  28         # Power
  29         register "PchPmSlpS3MinAssert" = "3" # 50ms
  30         register "PchPmSlpS4MinAssert" = "1" # 1s
  31         register "PchPmSlpSusMinAssert" = "4" # 4s
  32         register "PchPmSlpAMinAssert" = "4" # 2s
  33
  34         # Thermal
  35         register "tcc_offset" = "8"
  36
  37         # Serial IRQ Continuous
  38         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  39
  40 # PM Util (soc/intel/cannonlake/pmutil.c)
  41         # GPE configuration
  42         # Note that GPE events called out in ASL code rely on this
  43         # route. i.e. If this route changes then the affected GPE
  44         # offset bits also need to be changed.
  45         register "gpe0_dw0" = "PMC_GPP_K"
  46         register "gpe0_dw1" = "PMC_GPP_G"
  47         register "gpe0_dw2" = "PMC_GPP_E"
  48
  49 # Actual device tree
  50         device cpu_cluster 0 on end
  51
  52         device domain 0 on
  53                 device pci 00.0 on  end # Host Bridge
  54                 device pci 01.0 on      # GPU Port
  55                         # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
  56                         register "PcieClkSrcUsage[8]" = "0x40"
  57                         register "PcieClkSrcClkReq[8]" = "8"
  58                 end
  59                 device pci 02.0 on      # Integrated Graphics Device
  60                         register "gfx" = "GMA_DEFAULT_PANEL(0)"
  61                 end
  62                 device pci 04.0 on      # SA Thermal device
  63                         register "Device4Enable" = "1"
  64                 end
  65                 device pci 12.0 on  end # Thermal Subsystem
  66                 device pci 12.5 off end # UFS SCS
  67                 device pci 12.6 off end # GSPI #2
  68                 device pci 13.0 off end # Integrated Sensor Hub
  69                 device pci 14.0 on      # USB xHCI
  70                         # USB2
  71                         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
  72                         register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
  73                         register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
  74                         register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left
  75                         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
  76                         register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
  77                         register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
  78                         # USB3
  79                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
  80                         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
  81                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
  82                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
  83                 end
  84                 device pci 14.1 off end # USB xDCI (OTG)
  85                 device pci 14.2 on  end # Shared SRAM
  86                 device pci 14.3 on      # CNVi wifi
  87                         chip drivers/wifi/generic
  88                                 register "wake" = "GPE0_PME_B0"
  89                                 device generic 0 on end
  90                         end
  91                 end
  92                 device pci 14.5 off end # SDCard
  93                 device pci 15.1 on  end # I2C #1
  94                 device pci 15.2 off end # I2C #2
  95                 device pci 15.3 off end # I2C #3
  96                 device pci 16.0 on  end # Management Engine Interface 1
  97                 device pci 16.1 off end # Management Engine Interface 2
  98                 device pci 16.2 off end # Management Engine IDE-R
  99                 device pci 16.3 off end # Management Engine KT Redirection
 100                 device pci 16.4 off end # Management Engine Interface 3
 101                 device pci 16.5 off end # Management Engine Interface 4
 102                 device pci 17.0 on      # SATA
 103                         register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
 104                         register "SataPortsEnable[4]" = "1" # HDD (SATA4)
 105                 end
 106                 device pci 19.0 off end # I2C #4
 107                 device pci 19.1 off end # I2C #5
 108                 device pci 19.2 on  end # UART #2
 109                 device pci 1a.0 off end # eMMC
 110                 device pci 1b.0 off end # PCI Express Port 17
 111                 device pci 1b.1 off end # PCI Express Port 18
 112                 device pci 1b.2 off end # PCI Express Port 19
 113                 device pci 1b.3 off end # PCI Express Port 20
 114                 device pci 1b.4 on      # PCI Express Port 21
 115                         # PCI Express root port #21 x4, Clock 11 (SSD2)
 116                         register "PcieRpEnable[20]" = "1"
 117                         register "PcieRpLtrEnable[20]" = "1"
 118                         register "PcieClkSrcUsage[11]" = "20"
 119                         register "PcieClkSrcClkReq[11]" = "11"
 120                         register "PcieRpSlotImplemented[20]" = "1"
 121                 end
 122                 device pci 1b.5 off end # PCI Express Port 22
 123                 device pci 1b.6 off end # PCI Express Port 23
 124                 device pci 1b.7 off end # PCI Express Port 24
 125                 device pci 1c.0 off end # PCI Express Port 1
 126                 device pci 1c.1 off end # PCI Express Port 2
 127                 device pci 1c.2 off end # PCI Express Port 3
 128                 device pci 1c.3 off end # PCI Express Port 4
 129                 device pci 1c.4 off end # PCI Express Port 5
 130                 device pci 1c.5 off end # PCI Express Port 6
 131                 device pci 1c.6 off end # PCI Express Port 7
 132                 device pci 1c.7 off end # PCI Express Port 8
 133                 device pci 1d.0 on      # PCI Express Port 9
 134                         # PCI Express root port #9 x4, Clock 10 (SSD)
 135                         register "PcieRpEnable[8]" = "1"
 136                         register "PcieRpLtrEnable[8]" = "1"
 137                         register "PcieClkSrcUsage[10]" = "8"
 138                         register "PcieClkSrcClkReq[10]" = "10"
 139                         register "PcieRpSlotImplemented[8]" = "1"
 140                 end
 141                 device pci 1d.1 off end # PCI Express Port 10
 142                 device pci 1d.2 off end # PCI Express Port 11
 143                 device pci 1d.3 off end # PCI Express Port 12
 144                 device pci 1d.4 off end # PCI Express Port 13
 145                 device pci 1d.5 on      # PCI Express Port 14
 146                         # PCI Express root port #14 x1, Clock 6 (WLAN)
 147                         register "PcieRpEnable[13]" = "1"
 148                         register "PcieRpLtrEnable[13]" = "1"
 149                         register "PcieClkSrcUsage[6]" = "13"
 150                         register "PcieClkSrcClkReq[6]" = "6"
 151                         register "PcieRpSlotImplemented[13]" = "1"
 152                 end
 153                 device pci 1d.6 on      # PCI Express Port 15
 154                         # PCI Express root port #15 x1, Clock 5 (LAN)
 155                         register "PcieRpEnable[14]" = "1"
 156                         register "PcieRpLtrEnable[14]" = "1"
 157                         register "PcieClkSrcUsage[5]" = "14"
 158                         register "PcieClkSrcClkReq[5]" = "5"
 159                         register "PcieRpSlotImplemented[14]" = "1"
 160                 end
 161                 device pci 1d.7 off end # PCI Express Port 16
 162                 device pci 1e.0 off end # UART #0
 163                 device pci 1e.1 off end # UART #1
 164                 device pci 1e.2 off end # GSPI #0
 165                 device pci 1e.3 off end # GSPI #1
 166                 device pci 1f.0 on      # LPC Interface
 167                         register "gen1_dec" = "0x00040069"
 168                         register "gen2_dec" = "0x00fc0e01"
 169                         register "gen3_dec" = "0x00fc0f01"
 170                         chip drivers/pc80/tpm
 171                                 device pnp 0c31.0 on end
 172                         end
 173                 end
 174                 device pci 1f.1 off end # P2SB
 175                 device pci 1f.2 hidden end # Power Management Controller
 176                 device pci 1f.3 on      # Intel HDA
 177                         register "PchHdaAudioLinkHda" = "1"
 178                         register "PchHdaAudioLinkDmic0" = "1"
 179                         register "PchHdaAudioLinkDmic1" = "1"
 180                 end
 181                 device pci 1f.4 on  end # SMBus
 182                 device pci 1f.5 on  end # PCH SPI
 183                 device pci 1f.6 off end # GbE
 184         end
 185 end