| commit | 2072296330b6a79b5a502361a44d64302ee671dd | |
| author | Tarun Tuli <taruntuli@google.com> | |
| Mon, 13 Feb 2023 16:41:36 +0000 (13 16:41 +0000) | ||
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | |
| Wed, 15 Feb 2023 02:14:15 +0000 (15 02:14 +0000) | ||
| tree | 26f8a5c6b1c71a864cac6f2237a8fdd3cfb1c15b | treesnapshot (tar.gz zip) |
| parent | 944aff2635314e7ae7da7f7d8dfc16fc75822ec1 | commitdiff |
mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHz
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.
For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.
BUG=b:264704732
TEST=Verified all timings meet spec now
Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.
For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.
BUG=b:264704732
TEST=Verified all timings meet spec now
Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| src/mainboard/google/brya/variants/agah/overridetree.cb | diffblobblamehistory |