| commit | 433343eaaa987432242909fe4b1b482d53b66b4a | |
| author | Bora Guvendik <bora.guvendik@intel.com> | |
| Mon, 24 Apr 2023 22:50:15 +0000 (24 15:50 -0700) | ||
| committer | Nick Vaccaro <nvaccaro@google.com> | |
| Thu, 13 Jul 2023 01:04:37 +0000 (13 01:04 +0000) | ||
| tree | d9c027444040d35cef6a1ad7d27a38b74fd53b1c | treesnapshot (tar.gz zip) |
| parent | 0cc560fd3cde1cef2fbe0946668633c1136bfa9f | commitdiff |
soc/intel/alderlake: Hook up UPD LowerBasicMemTestSize
Hook the newly exposed LowerBasicMemTestSize UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Hook the newly exposed LowerBasicMemTestSize UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
| src/soc/intel/alderlake/chip.h | diffblobblamehistory | |
| src/soc/intel/alderlake/romstage/fsp_params.c | diffblobblamehistory |