| commit | 530c6f9cc8dd2c0cd0c586d3d14f11cb8021242f | |
| author | Bora Guvendik <bora.guvendik@intel.com> | |
| Fri, 13 Oct 2017 22:15:48 +0000 (13 15:15 -0700) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Tue, 17 Oct 2017 22:49:43 +0000 (17 22:49 +0000) | ||
| tree | b89237270f18e4c66b93061f223b03317579e6f9 | treesnapshot (tar.gz zip) |
| parent | de897a6dba1bc6ce157aed8c00cc20642c5d6c59 | commitdiff |
intel/cannonlake_rvp: enable HS400
Set SCS emmc HS400 enable FSP parameter.
TEST=Boot to OS, verify HS400 SDHCI print
Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22008
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Set SCS emmc HS400 enable FSP parameter.
TEST=Boot to OS, verify HS400 SDHCI print
Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22008
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
| src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | diffblobblamehistory | |
| src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | diffblobblamehistory |