| commit | 809e70410197967aff1efe4531d695fb28d92d3f | |
| author | Subrata Banik <subratabanik@google.com> | |
| Fri, 20 Dec 2024 03:59:56 +0000 (20 09:29 +0530) | ||
| committer | Subrata Banik <subratabanik@google.com> | |
| Sat, 21 Dec 2024 07:42:37 +0000 (21 07:42 +0000) | ||
| tree | 0299fc97fdd07ddd86903e945498d065e138aaf7 | treesnapshot (tar.gz zip) |
| parent | 222ef676f98521f312b640b3dc58d8794c90da68 | commitdiff |
soc/intel/pantherlake: Rename GSPI2 to GSPI0A
Rename GSPI2 to GSPI0A to align with the latest Intel documentation
and platform specifications (doc: 815002)
BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.
Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Rename GSPI2 to GSPI0A to align with the latest Intel documentation
and platform specifications (doc: 815002)
BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.
Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
| src/soc/intel/pantherlake/chipset.cb | diffblobblamehistory | |
| src/soc/intel/pantherlake/include/soc/serialio.h | diffblobblamehistory |