| commit | a35b9282cf3bfcc416a17659b846a33ad5458e1c | |
| author | Felix Held <felix-coreboot@felixheld.de> | |
| Fri, 3 Feb 2023 00:42:52 +0000 (3 01:42 +0100) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Sat, 4 Feb 2023 19:12:24 +0000 (4 19:12 +0000) | ||
| tree | f66f221cbd280d960365d10fc2bd8b303d286fc6 | treesnapshot (tar.gz zip) |
| parent | bee5c6084cd7555beefd933e44f6c2b67365f563 | commitdiff |
soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
Now that the PCIe ports on device 1 are added, rename the aliases for
the PCIe ports on device 2 to have a common naming scheme. For phoenix
the device alias names are based on the device and function number the
bridge is connected to.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the PCIe ports on device 1 are added, rename the aliases for
the PCIe ports on device 2 to have a common naming scheme. For phoenix
the device alias names are based on the device and function number the
bridge is connected to.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/amd/birman/devicetree_phoenix.cb | diffblobblamehistory | |
| src/mainboard/amd/mayan/devicetree_phoenix.cb | diffblobblamehistory | |
| src/soc/amd/phoenix/chipset.cb | diffblobblamehistory |