soc/intel/common: Add RAMTOP size in ramtop_table

soc/intel/common: Add RAMTOP size in ramtop_table

This patch adds a new field, `size`, to the `ramtop_table` structure to
store the size of the RAMTOP region.

The RAMTOP size is calculated as the difference between the cbmem top
and the FSP reserved memory base address, aligned up to the nearest 4MB
boundary.

This change allows for more accurate tracking of the RAMTOP region and
improves compatibility with different memory configurations.

Previously, the RAMTOP size was always assumed to be 16MB. This could
lead to boot hangs on systems with different memory configurations,
where the actual RAMTOP size exceeded 16MB.

By dynamically calculating and storing the RAMTOP size, this patch
ensures that the correct memory range is used for intermediate
caching, preventing boot hangs and improving boot speed.

The `update_ramtop()` function is updated to write the calculated
RAMTOP size to CMOS along with the RAMTOP address.

The `early_ramtop_enable_cache_range()` function is also updated to
use the RAMTOP size from CMOS to set the correct MTRR range.

BUG=b:373290479
TEST=Built and booted successfully on various platforms. Verified that
the RAMTOP size is correctly calculated and stored in CMOS

Change-Id: I16d610c5791895b59da57d543c54da6621617912
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85003
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>