drivers/intel/fsp2_0: Add option to control debug log level using CBFS

drivers/intel/fsp2_0: Add option to control debug log level using CBFS

This commit relies on newly added Kconfig option,
USE_CBFS_FILE_OPTION_BACKEND, which allows controlling the FSP debug
log level using CBFS options (RAW binary files).

The default log-level is setup in coreboot while stitching the CBFS
option binaries depending upon the coreboot log-level.

Following files will be used to determine the log levels:

- fsp_pcd_debug_level: For the overall FSP debug log level.

- fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log
  level.

In absense of these files, the FSP console log-level is determine by
calling into fsp_map_console_log_level API.

The values in these files should correspond to the FSP_LOG_LEVEL_* enum
values.

This change allows for more flexibility in controlling the FSP debug log
level, especially in cases of debugging silicon firmware issues with a
debug AP FW binary.

This capability is particularly useful when debugging issues that
require examining both silicon and MRC logs simultaneously.

BUG=b:227151510
TEST=Able to control the FSP debug log based on CBFS options

To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files
with the desired log level, run:

```
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level

cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level
```

With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO
CBFS, both the silicon firmware and MRC behave as debug binaries.

To verify the presence of both log-level RAW CBFS binaries in the CBFS RO
slot, run:

```
sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_
```

This should output:

```
option/fsp_mrc_debug_level            0x88e40    raw                 8 none
option/fsp_pcd_debug_level            0x2a7400   raw                 8 none
```

Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86001
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>