| commit | cfb044322e0e712ae071453b2aed53a820d0d22f | |
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | |
| Thu, 27 Jan 2022 08:33:20 +0000 (27 09:33 +0100) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Thu, 3 Feb 2022 13:49:34 +0000 (3 13:49 +0000) | ||
| tree | 62ae0b8a88e9b1105511022cb7a5a2185111cb03 | treesnapshot (tar.gz zip) |
| parent | 3c965dc3ac650b96097693d17cf1b96aec63b981 | commitdiff |
mb/siemens/mc_ehl2: Disable PCIe RPs
With latest hardware revision only PCIe RP2 and RP7 are used on this
mainboard.
Change-Id: I7702c2b9058dde1c819cb1df8a68fd602f5997da
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
With latest hardware revision only PCIe RP2 and RP7 are used on this
mainboard.
Change-Id: I7702c2b9058dde1c819cb1df8a68fd602f5997da
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | diffblobblamehistory |