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mb/ocp/tiogapass: Fix GPIOs
[coreboot2.git] / src / mainboard / acer / aspire_vn7_572g / devicetree.cb
blob21661f905f87e8a2e560d4076c28c31046dcc794
1 ## SPDX-License-Identifier: GPL-2.0-only
2
3 chip soc/intel/skylake
4
5 # Intel Common SoC Config
6 #+-------------------+---------------------------+
7 #| Field | Value |
8 #+-------------------+---------------------------+
9 #| I2C0 | Touchscreen |
10 #| I2C1 | Touchpad |
11 #+-------------------+---------------------------+
12 register "common_soc_config" = "{
13 .i2c[0] = {
14 .speed = I2C_SPEED_FAST,
15 },
16 .i2c[1] = {
17 .speed = I2C_SPEED_FAST,
18 .speed_config[0] = {
19 .speed = I2C_SPEED_FAST,
20 .scl_lcnt = 128,
21 .scl_hcnt = 160,
22 .sda_hold = 30,
23 }
24 },
25 }"
26
27 # TODO: Drop once CB:55224 is merged
28 register "SerialIoDevMode" = "{
29 [PchSerialIoIndexI2C0] = PchSerialIoPci,
30 [PchSerialIoIndexI2C1] = PchSerialIoPci,
31 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
32 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
33 }"
34
35 device domain 0 on
36 subsystemid 0x1025 0x1037 inherit
37 device ref system_agent on
38 # Enable "Enhanced Intel SpeedStep"
39 register "eist_enable" = "true"
40
41 # Set the Thermal Control Circuit (TCC) activation value to 97C
42 # even though FSP integration guide says to set it to 100C for SKL-U
43 # (offset at 0), because when the TCC activates at 100C, the CPU
44 # will have already shut itself down from overheating protection.
45 register "tcc_offset" = "3" # TCC of 97C
46
47 register "SaGv" = "SaGv_Enabled"
48
49 # VR Slew rate setting for improving audible noise
50 register "AcousticNoiseMitigation" = "1"
51 register "SlowSlewRateForIa" = "3" # Fast/16
52 register "SlowSlewRateForGt" = "3" # Fast/16
53 register "SlowSlewRateForSa" = "0" # Fast/2
54 register "FastPkgCRampDisableIa" = "0"
55 register "FastPkgCRampDisableGt" = "0"
56 register "FastPkgCRampDisableSa" = "0"
57
58 # PL1, PL2 override 35W, PL4 override 43W
59 register "power_limits_config" = "{
60 .tdp_pl1_override = 35,
61 .tdp_pl2_override = 35,
62 .tdp_pl4 = 43,
63 }"
64
65 # ISL95857 VR
66 # Send VR specific command for PS4 exit issue
67 register "SendVrMbxCmd" = "2"
68 # Send VR mailbox command for IA/GT/SA rails
69 register "IslVrCmd" = "2"
70 end
71 device ref igpu on
72 register "panel_cfg" = "{
73 .up_delay_ms = 150, // T3
74 .down_delay_ms = 50, // T10
75 .cycle_delay_ms = 500, // T12
76 .backlight_on_delay_ms = 1, // T7
77 .backlight_off_delay_ms = 200, // T9
78 .backlight_pwm_hz = 1000,
79 }"
80
81 # IGD Displays; LFP and 3*EFP
82 # FIXME: VBT does not define EFP3, board has no EFP2?
83 register "gfx" = "{
84 .use_spread_spectrum_clock = 1,
85 .ndid = 4, .did = { 0x0400, 0x0300, 0x0301, 0x0302 }
86 }"
87
88 register "PrimaryDisplay" = "Display_Switchable"
89 end
90 device ref south_xhci on
91 register "usb2_ports[0]" = "{
92 .enable = 1,
93 .ocpin = OC_SKIP,
94 .tx_bias = USB2_BIAS_17MV,
95 .tx_emp_enable = USB2_DE_EMP_ON,
96 .pre_emp_bias = USB2_BIAS_28MV,
97 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
98 }" # Type-A Port (right)
99 register "usb2_ports[1]" = "{
100 .enable = 1,
101 .ocpin = OC_SKIP,
102 .tx_bias = USB2_BIAS_17MV,
103 .tx_emp_enable = USB2_DE_EMP_ON,
104 .pre_emp_bias = USB2_BIAS_28MV,
105 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
106 }" # Type-A Port (right)
107 register "usb2_ports[2]" = "{
108 .enable = 1,
109 .ocpin = OC_SKIP,
110 .tx_bias = USB2_BIAS_17MV,
111 .tx_emp_enable = USB2_DE_EMP_ON,
112 .pre_emp_bias = USB2_BIAS_28MV,
113 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
114 }" # Type-C Port
115 register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A Port (left)
116 register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
117 register "usb2_ports[5]" = "USB2_PORT_FLEX(OC_SKIP)" # Touchscreen
118 register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam
119 register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
120 register "usb2_ports[8]" = "USB2_PORT_FLEX(OC_SKIP)" # Finger-printer
121
122 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right); Capable of OTG
123 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
124 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
125 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
126 chip drivers/usb/acpi
127 register "desc" = ""Root Hub""
128 register "type" = "UPC_TYPE_HUB"
129 device usb 0.0 on
130 chip drivers/usb/acpi
131 register "desc" = ""USB2 Type-A Right""
132 register "type" = "UPC_TYPE_USB3_A"
133 register "group" = "ACPI_PLD_GROUP(0, 1)"
134 device usb 2.0 on end
135 end
136 chip drivers/usb/acpi
137 register "desc" = ""USB2 Type-A Right""
138 register "type" = "UPC_TYPE_USB3_A"
139 register "group" = "ACPI_PLD_GROUP(0, 2)"
140 device usb 2.1 on end
141 end
142 chip drivers/usb/acpi
143 register "desc" = ""USB2 Type-C""
144 register "type" = "UPC_TYPE_C_USB2_SS"
145 register "group" = "ACPI_PLD_GROUP(0, 3)"
146 device usb 2.2 on end
147 end
148 chip drivers/usb/acpi
149 register "desc" = ""USB2 Type-A Left""
150 register "type" = "UPC_TYPE_A"
151 register "group" = "ACPI_PLD_GROUP(0, 4)"
152 device usb 2.3 on end
153 end
154 chip drivers/usb/acpi
155 register "desc" = ""USB2 Bluetooth""
156 register "type" = "UPC_TYPE_UNUSED"
157 register "group" = "ACPI_PLD_GROUP(0, 5)"
158 device usb 2.4 on end
159 end
160 chip drivers/usb/acpi
161 register "desc" = ""USB2 Touchscreen""
162 register "type" = "UPC_TYPE_UNUSED"
163 register "group" = "ACPI_PLD_GROUP(0, 6)"
164 device usb 2.5 on end
165 end
166 chip drivers/usb/acpi
167 register "desc" = ""USB2 Webcam""
168 register "type" = "UPC_TYPE_UNUSED"
169 register "group" = "ACPI_PLD_GROUP(0, 7)"
170 device usb 2.6 on end
171 end
172 chip drivers/usb/acpi
173 register "desc" = ""USB2 SD""
174 register "type" = "UPC_TYPE_UNUSED"
175 register "group" = "ACPI_PLD_GROUP(0, 8)"
176 device usb 2.7 on end
177 end
178 chip drivers/usb/acpi
179 register "desc" = ""USB2 Finger-printer""
180 register "type" = "UPC_TYPE_UNUSED"
181 register "group" = "ACPI_PLD_GROUP(0, 9)"
182 device usb 2.8 on end
183 end
184 chip drivers/usb/acpi
185 register "desc" = ""USB3 Type-A Right""
186 register "type" = "UPC_TYPE_USB3_A"
187 register "group" = "ACPI_PLD_GROUP(0, 1)"
188 device usb 3.0 on end
189 end
190 chip drivers/usb/acpi
191 register "desc" = ""USB3 Type-A Right""
192 register "type" = "UPC_TYPE_USB3_A"
193 register "group" = "ACPI_PLD_GROUP(0, 2)"
194 device usb 3.1 on end
195 end
196 chip drivers/usb/acpi
197 register "desc" = ""USB3 Type-C""
198 register "type" = "UPC_TYPE_C_USB2_SS"
199 register "group" = "ACPI_PLD_GROUP(0, 3)"
200 device usb 3.2 on end
201 end
202 chip drivers/usb/acpi
203 register "desc" = ""USB3 Type-C""
204 register "type" = "UPC_TYPE_C_USB2_SS"
205 register "group" = "ACPI_PLD_GROUP(0, 3)"
206 device usb 3.3 on end
207 end
208 end
209 end
210 end
211 device ref thermal on end
212 device ref i2c0 on
213 chip drivers/i2c/hid
214 register "generic.name" = ""TPL0""
215 register "generic.hid" = ""ELAN2259""
216 register "generic.desc" = ""ELAN Touchscreen""
217 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
218 register "generic.device_present_gpio" = "GPP_B15"
219 register "hid_desc_reg_offset" = "0x01"
220 device i2c 0x10 on end
221 end
222 end
223 device ref i2c1 on
224 chip drivers/i2c/hid
225 register "generic.name" = ""TPD0""
226 register "generic.hid" = ""SYN1B7F""
227 register "generic.desc" = ""Synaptics Touchpad""
228 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
229 # register "generic.wake" = "GPE0_DW2_16" # FIXME: Use EC's GPE?
230 register "generic.detect" = "1"
231 register "hid_desc_reg_offset" = "0x20"
232 device i2c 0x2c on end
233 end
234 chip drivers/i2c/hid
235 register "generic.name" = ""TPD1""
236 register "generic.hid" = ""ELAN0501""
237 register "generic.desc" = ""ELAN Touchpad""
238 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
239 register "generic.detect" = "1"
240 register "hid_desc_reg_offset" = "0x01"
241 device i2c 0x15 on end
242 end
243 end
244 device ref heci1 on end
245 device ref sata on
246 register "SataSalpSupport" = "1"
247 register "SataPortsEnable[1]" = "1" # HDD; BIT1 in 92h-93h
248 register "SataPortsEnable[2]" = "1" # ODD; BIT2 in 92h-93h
249 end
250 device ref uart2 on end
251 # Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text)
252 device ref pcie_rp1 on
253 # dGPU; x4
254 register "PcieRpEnable[0]" = "1"
255 register "PcieRpAdvancedErrorReporting[0]" = "1"
256 register "PcieRpLtrEnable[0]" = "1"
257 register "PcieRpClkReqSupport[0]" = "1"
258 register "PcieRpClkReqNumber[0]" = "0"
259 register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
260 end
261 device ref pcie_rp7 on
262 # NGFF; x2
263 register "PcieRpEnable[6]" = "1"
264 register "PcieRpAdvancedErrorReporting[6]" = "1"
265 register "PcieRpLtrEnable[6]" = "1"
266 register "PcieRpClkReqSupport[6]" = "1"
267 register "PcieRpClkReqNumber[6]" = "3"
268 register "PcieRpMaxPayload[6]" = "RpMaxPayload_256"
269 end
270 device ref pcie_rp9 on
271 # LAN
272 register "PcieRpEnable[8]" = "1"
273 register "PcieRpAdvancedErrorReporting[8]" = "1"
274 register "PcieRpLtrEnable[8]" = "1"
275 register "PcieRpClkReqSupport[8]" = "1"
276 register "PcieRpClkReqNumber[8]" = "1"
277 register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
278 end
279 device ref pcie_rp10 on
280 # WLAN
281 register "PcieRpEnable[9]" = "1"
282 register "PcieRpAdvancedErrorReporting[9]" = "1"
283 register "PcieRpLtrEnable[9]" = "1"
284 register "PcieRpClkReqSupport[9]" = "1"
285 register "PcieRpClkReqNumber[9]" = "2"
286 register "PcieRpMaxPayload[9]" = "RpMaxPayload_256"
287 # ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
288 register "pcie_rp_aspm[9]" = "AspmL1"
289 end
290 # Although vendor's platform NVS area shows SCS is enabled, the SD card reader is actually connected over USB
291 device ref lpc_espi on
292 register "lpc_iod" = "0x0010" # 80h-81h; ComB: 2F8h-2FFh (COM 2)
293 register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_KBC_60_64
294 | LPC_IOE_EC_62_66 | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F" # 82h-83h
295 register "gen3_dec" = "0x00040069" # 8Ch-8Fh; EC (sideband): Port 68h/6Ch
296 register "gen4_dec" = "0x000c1201" # 90h-93h; EC (index): Port 1200h
297
298 # EC/KBC requires continuous mode
299 register "serirq_mode" = "SERIRQ_CONTINUOUS"
300 end
301 device ref pmc on
302 # Note that GPE events called out in ASL code rely on this
303 # route. i.e. If this route changes then the affected GPE
304 # offset bits also need to be changed.
305 register "gpe0_dw0" = "GPP_C" # 3:0 in pwrmbase+0120h
306 register "gpe0_dw1" = "GPP_D" # 7:4 in pwrmbase+0120h
307 register "gpe0_dw2" = "GPP_E" # 11:8 in pwrmbase+0120h
308
309 # Enable S0ix
310 register "s0ix_enable" = true
311
312 register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h
313 register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h
314 register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" # 19:18 in pmbase+0018h
315 register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h
316 end
317 device ref hda on
318 register "DspEnable" = "1"
319 # PchHdaDspEndpointDmic is only to be returned to reference code
320 # DXE phase as HOB, used to select blob for NHLT
321 end
322 device ref smbus on end
323 device ref fast_spi on end
324 end
325 chip drivers/crb
326 device mmio 0xfed40000 on end
327 end
328 end
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