src/mainboard/amd/bilby/early_gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <gpio.h>
   4 #include "gpio.h"
   5
   6 /* GPIO pins used by coreboot should be initialized in bootblock */
   7
   8 static const struct soc_amd_gpio gpio_set_stage_reset[] = {
   9         /* assert PCIe reset */
  10         PAD_GPO(GPIO_6, HIGH),
  11         /* not LLB */
  12         PAD_GPI(GPIO_12, PULL_UP),
  13         /* not USB_OC1_L */
  14         PAD_GPI(GPIO_17, PULL_UP),
  15         /* not USB_OC2_L */
  16         PAD_GPI(GPIO_18, PULL_UP),
  17         /* SDIO eMMC power control */
  18         PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE),
  19         /* PCIe Reset to DP0, DP1, J2105, TP, FP */
  20         PAD_GPO(GPIO_27, HIGH),
  21         /* eSPI CS# */
  22         PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
  23         /* GPP_10G_SELECT => High=10G, Low=x2 NVME (work with AGPIO89) */
  24         PAD_GPO(GPIO_42, LOW),
  25         /* FANOUT0 */
  26         PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
  27         /* APU_COMBO_GPP_SW => High=SATA, Low=x2 NVME (work with EGPIO42) */
  28         PAD_GPO(GPIO_89, LOW),
  29         /* PC beep to codec */
  30         PAD_NF(GPIO_91, SPKR, PULL_NONE),
  31 };
  32
  33 void mainboard_program_early_gpios(void)
  34 {
  35         gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
  36 }