src/mainboard/intel/adlrvp/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config BOARD_INTEL_ADLRVP_COMMON
   4         def_bool n
   5         select BOARD_ROMSIZE_KB_32768
   6         select CPU_INTEL_SOCKET_LGA1700
   7         select DRIVERS_I2C_GENERIC
   8         select DRIVERS_I2C_HID
   9         select DRIVERS_I2C_MAX98373
  10         select DRIVERS_INTEL_DPTF
  11         select DRIVERS_INTEL_MIPI_CAMERA
  12         select DRIVERS_INTEL_SOUNDWIRE
  13         select DRIVERS_SOUNDWIRE_ALC711
  14         select DRIVERS_SPI_ACPI
  15         select DRIVERS_USB_ACPI
  16         select HAVE_ACPI_RESUME
  17         select HAVE_ACPI_TABLES
  18         select HAVE_SPD_IN_CBFS
  19         select MAINBOARD_HAS_CHROMEOS
  20         select SOC_INTEL_COMMON_BLOCK_IPU
  21         select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
  22
  23 config BOARD_INTEL_ADLRVP_P
  24         select BOARD_INTEL_ADLRVP_COMMON
  25         select DRIVERS_UART_8250IO
  26         select MAINBOARD_USES_IFD_EC_REGION
  27         select SOC_INTEL_ALDERLAKE_PCH_P
  28         select GEN3_EXTERNAL_CLOCK_BUFFER
  29         select MAINBOARD_USES_IFD_GBE_REGION
  30
  31 config BOARD_INTEL_ADLRVP_P_EXT_EC
  32         select BOARD_INTEL_ADLRVP_COMMON
  33         select DRIVERS_INTEL_PMC
  34         select INTEL_LPSS_UART_FOR_CONSOLE
  35         select SOC_INTEL_ALDERLAKE_PCH_P
  36         select GEN3_EXTERNAL_CLOCK_BUFFER
  37         select DRIVERS_WWAN_FM350GL
  38
  39 config BOARD_INTEL_ADLRVP_RPL
  40         select BOARD_INTEL_ADLRVP_COMMON
  41         select DRIVERS_UART_8250IO
  42         select GEN3_EXTERNAL_CLOCK_BUFFER
  43         select MAINBOARD_USES_IFD_EC_REGION
  44         select SOC_INTEL_ALDERLAKE_PCH_P
  45         select SOC_INTEL_RAPTORLAKE
  46
  47 config BOARD_INTEL_ADLRVP_RPL_EXT_EC
  48         select SOC_INTEL_RAPTORLAKE
  49         select BOARD_INTEL_ADLRVP_COMMON
  50         select DRIVERS_INTEL_PMC
  51         select INTEL_LPSS_UART_FOR_CONSOLE
  52         select SOC_INTEL_ALDERLAKE_PCH_P
  53         select GEN3_EXTERNAL_CLOCK_BUFFER
  54         select DRIVERS_WWAN_FM350GL
  55         select MAINBOARD_HAS_TPM2
  56         select SPI_TPM
  57         select TPM_GOOGLE_CR50
  58
  59 config BOARD_INTEL_ADLRVP_P_MCHP
  60         select BOARD_INTEL_ADLRVP_COMMON
  61         select DRIVERS_INTEL_MIPI_CAMERA
  62         select DRIVERS_INTEL_PMC
  63         select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
  64         select EC_GOOGLE_CHROMEEC_MEC
  65         select INTEL_LPSS_UART_FOR_CONSOLE
  66         select SOC_INTEL_ALDERLAKE_PCH_P
  67
  68 config BOARD_INTEL_ADLRVP_N
  69         select BOARD_INTEL_ADLRVP_COMMON
  70         select DRIVERS_UART_8250IO
  71         select MAINBOARD_USES_IFD_EC_REGION
  72         select SOC_INTEL_ALDERLAKE_PCH_N
  73
  74 config BOARD_INTEL_ADLRVP_N_EXT_EC
  75         select BOARD_INTEL_ADLRVP_COMMON
  76         select DRIVERS_INTEL_PMC
  77         select INTEL_LPSS_UART_FOR_CONSOLE
  78         select SOC_INTEL_ALDERLAKE_PCH_N
  79         select FW_CONFIG
  80         select FW_CONFIG_SOURCE_CHROMEEC_CBI
  81
  82 if BOARD_INTEL_ADLRVP_COMMON
  83
  84 config SOC_INTEL_CSE_LITE_SKU
  85         bool "Use CSE Lite firmware"
  86         default y if ADL_CHROME_EC
  87         help
  88           Enable if CSE Lite firmware is used in your build. It is commonly
  89           used in Chrome boards (chromebooks, chromeboxes, ...).
  90           But since ADL RVP build can be used with or without CSE Lite firmware
  91           it is a configurable option. Alderlake RVP boards usually don't use
  92           an CSE Lite firmware, but are still very likely to use it in case
  93           ChromeEC is used.
  94
  95 config CHROMEOS
  96         select GBB_FLAG_FORCE_DEV_SWITCH_ON
  97         select GBB_FLAG_FORCE_DEV_BOOT_USB
  98         select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
  99         select GBB_FLAG_FORCE_MANUAL_RECOVERY
 100         select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
 101         select HAS_RECOVERY_MRC_CACHE
 102
 103 config MAINBOARD_DIR
 104         default "intel/adlrvp"
 105
 106 config VARIANT_DIR
 107         default "adlrvp_p" if BOARD_INTEL_ADLRVP_P
 108         default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC
 109         default "adlrvp_rpl" if BOARD_INTEL_ADLRVP_RPL
 110         default "adlrvp_rpl_ext_ec" if BOARD_INTEL_ADLRVP_RPL_EXT_EC
 111         default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP
 112         default "adlrvp_n" if BOARD_INTEL_ADLRVP_N
 113         default "adlrvp_n_ext_ec" if BOARD_INTEL_ADLRVP_N_EXT_EC
 114
 115 config GBB_HWID
 116         string
 117         depends on CHROMEOS
 118         default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
 119         default "ADLRVPP TEST 2418"
 120
 121 config MAINBOARD_PART_NUMBER
 122         default "Alder Lake Client"
 123
 124 config MAINBOARD_VENDOR
 125         string
 126         default "Intel Corporation"
 127
 128 config MAINBOARD_FAMILY
 129         string
 130         default "Intel_adlrvp"
 131
 132 config DEVICETREE
 133         default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
 134         default "devicetree.cb"
 135
 136 config OVERRIDE_DEVICETREE
 137         default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 138
 139 choice
 140         prompt "ON BOARD EC"
 141         default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC
 142         help
 143           This option allows you to select the on board EC to use.
 144           Select whether the board has Intel EC or Chrome EC
 145
 146 config ADL_CHROME_EC
 147         bool "Chrome EC"
 148         select EC_GOOGLE_CHROMEEC
 149         select EC_GOOGLE_CHROMEEC_ESPI
 150         select EC_GOOGLE_CHROMEEC_BOARDID
 151         select EC_ACPI
 152         select EC_GOOGLE_CHROMEEC_LPC
 153
 154 config ADL_INTEL_EC
 155         bool "Intel EC"
 156         select EC_ACPI
 157 endchoice
 158
 159 config VBOOT
 160         select VBOOT_LID_SWITCH
 161         select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
 162         select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
 163         select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC
 164
 165 config UART_FOR_CONSOLE
 166         int
 167         default 0
 168
 169 config DRIVER_TPM_SPI_BUS
 170         default 0x2 if BOARD_INTEL_ADLRVP_RPL_EXT_EC
 171
 172 config USE_PM_ACPI_TIMER
 173         default n if BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_N
 174
 175 config TPM_TIS_ACPI_INTERRUPT
 176         int
 177         default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3)
 178
 179 config GEN3_EXTERNAL_CLOCK_BUFFER
 180         bool
 181         depends on SOC_INTEL_ALDERLAKE_PCH_P
 182         default n
 183         help
 184           Support external Gen-3 clock chip for ADL-P.
 185           `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer
 186           for further distribution to platform. SRCCLKREQB[7:9] maps to internal
 187           SRCCLKREQB[6]. If any of them asserted, SRC buffer
 188           `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled.
 189
 190 config CLKSRC_FOR_EXTERNAL_BUFFER
 191         depends on GEN3_EXTERNAL_CLOCK_BUFFER
 192         int
 193         default 6  # CLKSRC 6
 194 endif