src/mainboard/intel/adlrvp/gpio_m.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <vendorcode/google/chromeos/chromeos.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config gpio_table[] = {
  10         /* A12 : BT_RF_KILL_N */
  11         PAD_CFG_GPO(GPP_A12, 1, PLTRST),
  12
  13         /* H2 : WLAN_RST_N */
  14         PAD_CFG_GPO(GPP_H2, 1, PLTRST),
  15         /* 8 : M.2_BTWIFI_SUS_CLK */
  16         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
  17         /* 9 : GPD_9_SLP_WLAN_N */
  18         PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
  19         /* 10 : GPD_10_SLP_S5_N */
  20         PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
  21
  22         /* D12 : WIFI_RF_KILL_N */
  23         PAD_CFG_GPO(GPP_D12, 1, PLTRST),
  24         /* D13 : WIFI_WAKE_N */
  25         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
  26         /* D14 :  x1 PCIE slot1 PWREN / SML0B_CLK */
  27         PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
  28         /* D15 : WWAN_DISABLE_N */
  29         PAD_CFG_GPO(GPP_D15, 1, PLTRST),
  30         /* D17 : PCIE SLOT1 WAKE N */
  31         PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, DEEP, LEVEL, INVERT),
  32         /* D18 : WWAN WAKE N*/
  33         PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
  34         /* H23 : CLKREQ5_WWAN_N */
  35         PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
  36
  37         /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
  38         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
  39         /* F1 : CNV_BRI_RSP_BT_UART2_RXD */
  40         PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
  41         /* F2 : CNV_RGI_DT_BT_UART2_TXD */
  42         PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
  43         /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
  44         PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
  45         /* F4 : CNV_RF_RESET_R_N */
  46         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
  47         /* F5 : MODEM_CLKREQ_R */
  48         PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
  49         /* F6 : GPPC_F6_CNV_PA_BLANKING */
  50         PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
  51         /* F10 : GPPC_F10 X1_Slot_RESET */
  52         PAD_CFG_GPO(GPP_F10, 1, PLTRST),
  53         /* H8 : CNV_MFUART2_RXD */
  54         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
  55         /* H9 : CNV_MFUART2_TXD */
  56         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
  57
  58         /* A14 : TCPC01_TYPEA23_OC1_N */
  59         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  60         /* A15 :  USB_TYPEA_OC2_N */
  61         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  62         /* E18 : TBT_LSX0_TXD */
  63         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
  64         /* E19 : TBT_LSX0_RXD */
  65         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
  66         /* E20 : TBT_LSX1_TXD */
  67         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
  68         /* E21 : TBT_LSX1_RXD */
  69         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
  70
  71         /* H4  : I2C0 SDA */
  72         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  73         /* H6  : I2C1 SDA */
  74         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
  75         /* B16 : I2C5 SDA */
  76         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
  77
  78         /* H5  : I2C0 SCL */
  79         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  80         /* H7  : I2C1 SCL */
  81         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
  82         /* B17 : I2C5 SCL */
  83         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
  84
  85         /* C5  : WWAN_PERST_N */
  86         PAD_CFG_GPO(GPP_C5, 1, PLTRST),
  87         /* E5  : WWAN_PERST# */
  88         PAD_CFG_GPO(GPP_E5, 1, PLTRST),
  89         /* D15 : WWAN_DISABLE_N */
  90         PAD_CFG_GPO(GPP_D15, 1, PLTRST),
  91         /* D9  : WWAN_FCP_POWER_OFF_N */
  92         PAD_CFG_GPO(GPP_D9, 1, PLTRST),
  93
  94         /* H0  : PCH_SSD_RST# */
  95         PAD_CFG_GPO(GPP_H0, 1, PLTRST),
  96         /* H13 : CPU_SSD_RST# */
  97         PAD_CFG_GPO(GPP_H13, 1, PLTRST),
  98
  99         /* DDP1/2/A/B  CTRLCLK and CTRLDATA pins */
 100         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
 101         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
 102         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
 103         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
 104         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
 105         PAD_CFG_NF(GPP_E23, NONE, DEEP, NF2),
 106         PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
 107         PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
 108         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 109         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 110
 111         /* HPD_1 (E14) and HPD_2 (A18) pins */
 112         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 113         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 114
 115         PAD_NC(GPP_A19, NONE),
 116         PAD_NC(GPP_A20, NONE),
 117
 118         /* GPIO pin for PCIE SRCCLKREQB */
 119         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 120         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 121         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 122         PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 123         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 124
 125         /* CAM1_RST */
 126         PAD_CFG_GPO(GPP_R5, 1, PLTRST),
 127         /* CAM2_RST */
 128         PAD_CFG_GPO(GPP_E15, 1, PLTRST),
 129         /* CAM1_PWR_EN */
 130         PAD_CFG_GPO(GPP_B23, 1, PLTRST),
 131         /* CAM2_PWR_EN */
 132         PAD_CFG_GPO(GPP_E16, 1, PLTRST),
 133         /* IMGCLKOUT0 */
 134         PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
 135         /* IMGCLKOUT1 */
 136         PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
 137
 138         /* C16 : I2C0 SDA */
 139         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 140
 141         /* S0 : SNDW1_CLK */
 142         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
 143
 144         /* S1 : SNDW1_DATA */
 145         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
 146
 147         /* S2 : SNDW2_CLK */
 148         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
 149
 150         /* S3 : SNDW2_DATA */
 151         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
 152
 153         /* S4 : SNDW3_CLK */
 154         PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
 155
 156         /* S5 : SNDW3_DATA */
 157         PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
 158
 159         /* S6 : SNDW4_CLK */
 160         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
 161
 162         /* S7 : SNDW4_DATA */
 163         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
 164
 165         /* F7  : TCH_PNL_PWR_EN */
 166         PAD_CFG_GPO(GPP_F7, 1, PLTRST),
 167         /* F17 : RST_N_TCH_PNL2 */
 168         PAD_CFG_GPO(GPP_F17, 1, PLTRST),
 169         /* F18 : INT_N_TCH_PNL2 */
 170         PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
 171
 172         /* E3 : H1_PCH_INT_ODL */
 173         PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
 174
 175         /* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
 176         PAD_CFG_GPO(GPP_E4, 0, DEEP),
 177
 178         /* H1 : GPPC_H1_TCH_PAD_TCH_PNL2_LS_EN */
 179         PAD_CFG_GPO(GPP_H1, 0, PLTRST),
 180
 181         /* D11 : TCH_PAD_INT_N */
 182         PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST, LEVEL, INVERT)
 183 };
 184
 185 void variant_configure_gpio_pads(void)
 186 {
 187         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 188 }
 189
 190 static const struct cros_gpio cros_gpios[] = {
 191         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 192 };
 193 DECLARE_CROS_GPIOS(cros_gpios);