mb/ocp/tiogapass: Fix GPIOs
[coreboot2.git] / src / mainboard / intel / avenuecity_crb / bootblock.c
blobe68d874c900ec49fdcc50198be29bfd026d24a56
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootblock_common.h>
4 #include <console/console.h>
5 #include <intelblocks/lpc_lib.h>
6 #include <soc/intel/common/block/lpc/lpc_def.h>
7 #include <superio/aspeed/ast2400/ast2400.h>
8 #include <superio/aspeed/common/aspeed.h>
10 #define ASPEED_SIO_PORT 0x2E
12 void bootblock_mainboard_early_init(void)
14 /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */
15 lpc_io_setup_comm_a_b();
16 lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F);
18 if (CONFIG_UART_FOR_CONSOLE == 0) {
19 /* Setup superio com1 */
20 const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
21 aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
22 } else
23 die("COMs other than COM1 not supported\n");