src/mainboard/intel/coffeelake_rvp/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <baseboard/gpio.h>
   5 #include <gpio.h>
   6 #include <soc/cnl_memcfg_init.h>
   7
   8 static const struct cnl_mb_cfg baseboard_memcfg_cfg = {
   9         /* Access memory info through SMBUS. */
  10         .spd[0] = {
  11                 .read_type = READ_SMBUS,
  12                 .spd_spec = {.spd_smbus_address = 0xA0}
  13         },
  14         .spd[1] = {
  15                 .read_type = READ_SMBUS,
  16                 .spd_spec = {.spd_smbus_address = 0xA2}
  17         },
  18         .spd[2] = {
  19                 .read_type = READ_SMBUS,
  20                 .spd_spec = {.spd_smbus_address = 0xA4}
  21         },
  22         .spd[3] = {
  23                 .read_type = READ_SMBUS,
  24                 .spd_spec = {.spd_smbus_address = 0xA6}
  25         },
  26         /*
  27          * The dqs_map arrays map the ddr4 pins to the SoC pins
  28          * for both channels.
  29          *
  30          * the index = pin number on ddr4 part
  31          * the value = pin number on SoC
  32          */
  33         .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7},
  34         .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7},
  35
  36         /* Baseboard uses 121, 81 and 100 rcomp resistors */
  37         .rcomp_resistor = {121, 81, 100},
  38
  39         /*
  40          * Baseboard Rcomp target values.
  41          */
  42         .rcomp_targets = {100, 40, 20, 20, 26},
  43
  44         /* Baseboard is an interleaved design */
  45         .dq_pins_interleaved = 1,
  46
  47         /* Baseboard is using config 2 for vref_ca */
  48         .vref_ca_config = 2,
  49
  50         /* Disable Early Command Training */
  51         .ect = 0,
  52 };
  53
  54 const struct cnl_mb_cfg *__weak variant_memcfg_config(void)
  55 {
  56         return &baseboard_memcfg_cfg;
  57 }