src/mainboard/lenovo/m920q/devicetree.cb

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/cannonlake
   4         register "power_limits_config" = "{
   5                 .tdp_pl2_override = 65,
   6         }"
   7
   8         # Unmap unused CLKREQ lines, otherwise CLKSRC #0 won't work
   9         register "PcieClkSrcClkReq[1]"  = "PCIE_CLK_NOTUSED"
  10         register "PcieClkSrcClkReq[5]"  = "PCIE_CLK_NOTUSED"
  11         register "PcieClkSrcClkReq[7]"  = "PCIE_CLK_NOTUSED"
  12         register "PcieClkSrcClkReq[8]"  = "PCIE_CLK_NOTUSED"
  13         register "PcieClkSrcClkReq[9]"  = "PCIE_CLK_NOTUSED"
  14         register "PcieClkSrcClkReq[11]" = "PCIE_CLK_NOTUSED"
  15         register "PcieClkSrcClkReq[12]" = "PCIE_CLK_NOTUSED"
  16         register "PcieClkSrcClkReq[13]" = "PCIE_CLK_NOTUSED"
  17         register "PcieClkSrcClkReq[14]" = "PCIE_CLK_NOTUSED"
  18         register "PcieClkSrcClkReq[15]" = "PCIE_CLK_NOTUSED"
  19
  20         device domain 0 on
  21                 subsystemid 0x17aa 0x3136 inherit
  22                 # Slot JP3
  23                 device ref peg0                 on
  24                         register "PcieClkSrcUsage[0]"   = "0x40"
  25                         register "PcieClkSrcClkReq[0]"  = "0"
  26                 end
  27                 device ref igpu                 on      end
  28                 device ref dptf                 on      end
  29                 device ref thermal              on      end
  30                 device ref xhci                 on
  31                         register "usb2_ports" = "{
  32                                 [0] = USB2_PORT_MID(OC0),               // Internal USB header
  33                                 [1] = USB2_PORT_TYPE_C(OC1),            // Front port (charger)
  34                                 [3] = USB2_PORT_TYPE_C(OC2),            // Front Type C port
  35                                 [4] = USB2_PORT_MID(OC4),               // Rear USB 3.1 port 1
  36                                 [5] = USB2_PORT_MID(OC6),               // Rear USB 3.1 port 2
  37                                 [6] = USB2_PORT_MID(OC3),               // Rear USB 3.0 port 1
  38                                 [7] = USB2_PORT_MID(OC5),               // Rear USB 3.0 port 2
  39                                 [13] = USB2_PORT_SHORT(OC_SKIP),        // M.2 2230
  40                         }"
  41
  42                         register "usb3_ports" = "{
  43                                 [0] = USB3_PORT_DEFAULT(OC1),   // Front port (charger)
  44                                 [1] = USB3_PORT_DEFAULT(OC2),   // Front Type C port
  45                                 [2] = USB3_PORT_DEFAULT(OC4),   // Rear USB 3.1 port 1
  46                                 [3] = USB3_PORT_DEFAULT(OC6),   // Rear USB 3.2 port 2
  47                                 [4] = USB3_PORT_DEFAULT(OC3),   // Rear USB 3.0 port 1
  48                                 [5] = USB3_PORT_DEFAULT(OC5),   // Rear USB 3.0 port 2
  49                                 [6] = USB3_PORT_DEFAULT(OC0),   // Internal USB header
  50                         }"
  51                 end
  52                 device ref shared_sram  on      end
  53                 device ref cnvi_wifi    on
  54                         chip drivers/wifi/generic
  55                                 register "wake" = "PME_B0_EN_BIT"
  56                                 device generic 0 on end
  57                         end
  58                 end
  59                 device ref heci1        on      end
  60                 device ref heci3        on      end
  61                 device ref sata         on
  62                         register "SataSalpSupport" = "1"
  63                         register "SataPortsEnable" = "{
  64                                 [0] = 1, // on-board SATA1
  65                                 [4] = 1, // M.2 SATA on M920x
  66                         }"
  67                 end
  68
  69                 device ref pcie_rp6     on # WLAN
  70                         register "PcieRpEnable[5]"              = "1"
  71                         register "PcieRpSlotImplemented[5]"     = "1"
  72                         register "PcieClkSrcUsage[3]"           = "5"
  73                         register "PcieClkSrcClkReq[3]"          = "3"
  74                 end
  75
  76                 device ref pcie_rp9     on # PCIe x4
  77                         register "PcieRpEnable[8]"              = "1"
  78                         register "PcieRpSlotImplemented[8]"     = "1"
  79                         register "PcieClkSrcUsage[2]"           = "8"
  80                         register "PcieClkSrcClkReq[2]"          = "2"
  81                 end
  82
  83                 device ref pcie_rp17 on # M.2 SSD #2
  84                         register "PcieRpEnable[16]"             = "1"
  85                         register "PcieRpSlotImplemented[16]"    = "1"
  86                         register "PcieClkSrcUsage[10]"          = "16"
  87                         register "PcieClkSrcClkReq[10]"         = "10"
  88                 end
  89
  90                 device ref pcie_rp21 on # M.2 SSD #1
  91                         register "PcieRpEnable[20]"             = "1"
  92                         register "PcieRpSlotImplemented[20]"    = "1"
  93                         register "PcieClkSrcUsage[4]"           = "20"
  94                         register "PcieClkSrcClkReq[4]"          = "4"
  95                 end
  96
  97                 device ref lpc_espi     on
  98                         chip superio/nuvoton/nct6687d
  99                                 device pnp 2e.1 off     end     # Parallel port
 100                                 device pnp 2e.2 off     end     # UARTA (USB debug port?)
 101                                 device pnp 2e.3 on              # UARTB - COM1 header - optional sub-board
 102                                         io 0x60 = 0x3f8
 103                                         irq 0x70 = 4
 104                                         irq 0xf0 = 0
 105                                         irq 0xf1 = 0
 106                                 end
 107                                 device pnp 2e.5 off     end     # Keyboard
 108                                 device pnp 2e.6 off     end     # CIR
 109                                 device pnp 2e.7 off     end     # GPIO0-7
 110                                 device pnp 2e.8 off     end     # P80 UART
 111                                 device pnp 2e.9 off     end     # GPIO8-9, GPIO1-8 AF
 112                                 device pnp 2e.a on              # ACPI
 113                                         io 0x60 = 0x00
 114                                         irq 0x70 = 0x40
 115                                 end
 116                                 device pnp 2e.b on              # EC
 117                                         io 0x60 = 0xa20
 118                                         irq 0x70 = 0
 119                                 end
 120                                 device pnp 2e.c off     end     # RTC
 121                                 device pnp 2e.d off     end     # Deep Sleep
 122                                 device pnp 2e.e on              # TACH/PWM assignment
 123                                         irq 0xe4 = 0x10
 124                                         irq 0xe5 = 0x09
 125                                 end
 126                                 device pnp 2e.f off     end     # Function register
 127                         end
 128                         chip drivers/pc80/tpm
 129                                 device pnp 0c31.0 on    end
 130                         end
 131                 end
 132                 device ref hda  on
 133                         register "PchHdaAudioLinkHda"   = "1"
 134                 end
 135                 device ref smbus        on      end
 136                 device ref fast_spi     on      end
 137                 device ref gbe  on
 138                         register "PcieClkSrcUsage[6]"   = "PCIE_CLK_LAN"
 139                         register "PcieClkSrcClkReq[6]"  = "6"
 140                 end
 141         end
 142 end