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mb/ocp/tiogapass: Fix GPIOs
[coreboot2.git] / src / mainboard / msi / ms7d25 / devicetree.cb
blob73d871d34627d5acb83fc17adddbd1e485e67824
1 chip soc/intel/alderlake
2 # FSP configuration
3
4 register "eist_enable" = "true"
5
6 # Sagv Configuration
7 register "sagv" = "SaGv_Enabled"
8 register "RMT" = "0"
9 register "enable_c6dram" = "1"
10
11 register "pmc_gpe0_dw0" = "GPP_J"
12 register "pmc_gpe0_dw1" = "GPP_VPGIO"
13 register "pmc_gpe0_dw2" = "GPD"
14
15 # USB Configuration
16 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1
17 register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT
18 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1
19 register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5
20 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0
21 register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty?
22 register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4
23 register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4
24 register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3
25 register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3
26 register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1
27 register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1
28 register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers
29 register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT
30 register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1
31 register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2
32
33 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1
34 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
35 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
36 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
37 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
38 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
39 register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
40 register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
41 register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
42 register "usb3_ports[9]" = "USB3_PORT_EMPTY"
43
44 # LPC generic I/O ranges
45 register "gen1_dec" = "0x00fc0201"
46 register "gen2_dec" = "0x003c0a01"
47 register "gen3_dec" = "0x000c03f1"
48 register "gen4_dec" = "0x000c0081"
49
50 register "sata_salp_support" = "1"
51
52 register "sata_ports_enable" = "{
53 [0] = 1,
54 [1] = 1,
55 [2] = 1,
56 [3] = 1,
57 [4] = 1,
58 [5] = 1,
59 [6] = 1,
60 [7] = 1,
61 }"
62
63 register "sata_ports_dev_slp" = "{
64 [0] = 0,
65 [1] = 0,
66 [2] = 0,
67 [3] = 0,
68 [4] = 0,
69 [5] = 0,
70 [6] = 1,
71 [7] = 1,
72 }"
73
74 # HDMI on port B
75 register "ddi_portB_config" = "1"
76 register "ddi_ports_config" = "{
77 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
78 [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
79 [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
80 [DDI_PORT_2] = DDI_ENABLE_HPD,
81 [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
82 [DDI_PORT_4] = DDI_ENABLE_HPD,
83 }"
84
85 register "hybrid_storage_mode" = "true"
86 register "dmi_power_optimize_disable" = "true"
87
88 # FIVR configuration
89 register "fivr_rfi_frequency" = "1394"
90 register "fivr_spread_spectrum" = "FIVR_SS_1_5"
91 register "ext_fivr_settings" = "{
92 .configure_ext_fivr = 1,
93 }"
94
95 device domain 0 on
96 subsystemid 0x1462 0x7d25 inherit
97 device ref pcie5_0 on
98 register "cpu_pcie_rp[CPU_RP(2)]" = "{
99 .clk_src = 0,
100 .clk_req = 0,
101 .flags = PCIE_RP_LTR | PCIE_RP_AER,
102 }"
103 smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong"
104 "PCI_E1" "SlotDataBusWidth16X"
105 end
106 device ref pcie5_1 off end
107 device ref igpu on end
108 device ref pcie4_0 on
109 register "cpu_pcie_rp[CPU_RP(1)]" = "{
110 .clk_src = 9,
111 .clk_req = 9,
112 .flags = PCIE_RP_LTR | PCIE_RP_AER,
113 }"
114 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
115 "M2_1" "SlotDataBusWidth4X"
116 end
117 device ref crashlog off end
118 device ref xhci on end
119 device ref cnvi_wifi on
120 # Enable CNVi BT
121 register "cnvi_bt_core" = "true"
122 register "cnvi_bt_audio_offload" = "false"
123 chip drivers/wifi/generic
124 register "wake" = "GPE0_PME_B0"
125 register "enable_cnvi_ddr_rfim" = "true"
126 device generic 0 on end
127 end
128 end
129 device ref heci1 on end
130 device ref heci2 off end
131 device ref ide_r off end
132 device ref kt off end
133 device ref heci3 off end
134 device ref heci4 off end
135 device ref sata on end
136 device ref pcie_rp1 on
137 register "pch_pcie_rp[PCH_RP(1)]" = "{
138 .clk_src = 10,
139 .clk_req = 10,
140 .flags = PCIE_RP_LTR | PCIE_RP_AER,
141 }"
142 smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort"
143 "PCI_E2" "SlotDataBusWidth1X"
144 end
145 device ref pcie_rp2 on
146 register "pch_pcie_rp[PCH_RP(2)]" = "{
147 .clk_src = 17,
148 .clk_req = 17,
149 .flags = PCIE_RP_LTR | PCIE_RP_AER,
150 }"
151 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
152 "PCI_E4" "SlotDataBusWidth1X"
153 end
154 device ref pcie_rp3 on
155 # i225 Ethernet, Clock PM unsupported, onboard device
156 register "pch_pcie_rp[PCH_RP(3)]" = "{
157 .clk_src = 12,
158 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
159 }"
160 end
161 device ref pcie_rp4 off end
162
163 device ref pcie_rp5 on
164 register "pch_pcie_rp[PCH_RP(5)]" = "{
165 .clk_src = 15,
166 .clk_req = 15,
167 .flags = PCIE_RP_LTR | PCIE_RP_AER,
168 }"
169 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
170 "PCI_E3" "SlotDataBusWidth4X"
171 end
172
173 device ref pcie_rp9 on
174 register "pch_pcie_rp[PCH_RP(9)]" = "{
175 .clk_src = 13,
176 .clk_req = 13,
177 .flags = PCIE_RP_LTR | PCIE_RP_AER,
178 }"
179 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
180 "M2_3" "SlotDataBusWidth4X"
181 end
182
183 # These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports.
184 # There is an ASMedia switch on-board to mux the SATA ports 7, 8 and PCIe
185 # 9-12, 21-24 to M2_3 and M2_4 slots
186 device ref pcie_rp13 off end
187 device ref pcie_rp14 off end
188 device ref pcie_rp15 off end
189 device ref pcie_rp16 off end
190 device ref pcie_rp17 off end
191 device ref pcie_rp18 off end
192 device ref pcie_rp19 off end
193 device ref pcie_rp20 off end
194
195 device ref pcie_rp21 on
196 register "pch_pcie_rp[PCH_RP(21)]" = "{
197 .clk_src = 14,
198 .clk_req = 14,
199 .flags = PCIE_RP_LTR | PCIE_RP_AER,
200 }"
201 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
202 "M2_4" "SlotDataBusWidth4X"
203 end
204
205 device ref pcie_rp25 on
206 register "pch_pcie_rp[PCH_RP(25)]" = "{
207 .clk_src = 8,
208 .clk_req = 8,
209 .flags = PCIE_RP_LTR | PCIE_RP_AER,
210 }"
211 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
212 "M2_2" "SlotDataBusWidth4X"
213 end
214 device ref pch_espi on
215 chip superio/nuvoton/nct6687d
216 device pnp 4e.1 off end # Parallel port
217 device pnp 4e.2 on # COM1
218 io 0x60 = 0x3f8
219 irq 0x70 = 4
220 end
221 device pnp 4e.3 off end # COM2, IR
222 device pnp 4e.5 on # Keyboard
223 io 0x60 = 0x60
224 io 0x62 = 0x64
225 irq 0x70 = 1
226 irq 0x72 = 12
227 end
228 device pnp 4e.6 off end # CIR
229 device pnp 4e.7 off end # GPIO0-7
230 device pnp 4e.8 off end # P80 UART
231 device pnp 4e.9 off end # GPIO8-9, GPIO1-8 AF
232 device pnp 4e.a on # ACPI
233 # Vendor firmware did not assign I/O and IRQ
234 end
235 device pnp 4e.b on # EC
236 io 0x60 = 0xa20
237 # Vendor firmware did not assign IRQ
238 end
239 device pnp 4e.c off end # RTC
240 device pnp 4e.d off end # Deep Sleep
241 device pnp 4e.e off end # TACH/PWM assignment
242 device pnp 4e.f off end # Function register
243 end
244 chip drivers/pc80/tpm
245 device pnp 0.0 on end # TPM
246 end
247 end
248 device ref p2sb on end
249 device ref hda on
250 subsystemid 0x1462 0x9d25
251 register "pch_hda_audio_link_hda_enable" = "1"
252 register "pch_hda_dsp_enable" = "0"
253 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
254 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
255 register "pch_hda_idisp_codec_enable" = "true"
256 end
257 device ref smbus on end
258
259 chip drivers/crb
260 device mmio 0xfed40000 on end
261 end
262 end
263 end
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